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Date:   Fri, 4 Dec 2020 13:55:33 +0000
From:   Russell King - ARM Linux admin <linux@armlinux.org.uk>
To:     Steen Hegelund <steen.hegelund@microchip.com>
Cc:     Andrew Lunn <andrew@lunn.ch>,
        Kishon Vijay Abraham I <kishon@ti.com>,
        Vinod Koul <vkoul@kernel.org>,
        linux-arm-kernel@lists.infradead.org,
        Alexandre Belloni <alexandre.belloni@bootlin.com>,
        Lars Povlsen <lars.povlsen@microchip.com>,
        Bjarni Jonasson <bjarni.jonasson@microchip.com>,
        Microchip UNG Driver List <UNGLinuxDriver@microchip.com>,
        netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v8 3/4] phy: Add Sparx5 ethernet serdes PHY driver
Message-ID: <20201204135532.GK1551@shell.armlinux.org.uk>
References: <20201203103015.3735373-1-steen.hegelund@microchip.com>
 <20201203103015.3735373-4-steen.hegelund@microchip.com>
 <20201203215253.GL2333853@lunn.ch>
 <20201204134826.lnkdtj5nrygsngm2@mchp-dev-shegelun>
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Sender: Russell King - ARM Linux admin <linux@armlinux.org.uk>
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On Fri, Dec 04, 2020 at 02:48:26PM +0100, Steen Hegelund wrote:
> On 03.12.2020 22:52, Andrew Lunn wrote:
> > What i have not yet seen is how this code plugs together with
> > phylink_pcs_ops?
> > 
> > Can this hardware also be used for SATA, USB? As far as i understand,
> > the Marvell Comphy is multi-purpose, it is used for networking, USB,
> > and SATA, etc. Making it a generic PHY then makes sense, because
> > different subsystems need to use it.
> > 
> > But it looks like this is for networking only? So i'm wondering if it
> > belongs in driver/net/pcs and it should be accessed using
> > phylink_pcs_ops?
> > 
> >        Andrew
> 
> This is a PHY that communicates on a SerDes link to an ethernet PHY or a
> SFP. So I took the lead from earlier work: the Microsemi Ocelot SerDes driver,
> and added the Sparx5 SerDes PHY driver here since it is very similar in intent.
> It is not an ethernet PHY as such.

Okay, that is the normal situation in real hardware:

MAC <---> PCS PHY <---> SerDes PHY <---> SerDes lanes

where the PCS PHY handles the protocol level, and the SerDes PHY handles
the clocking and electrical characteristics of the SerDes lanes.

Maybe we should ask for a diagram of the setups when new support is
submitted to make the process of understanding the hardware easier?

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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