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Date:   Fri, 4 Dec 2020 19:35:17 -0800
From:   mark gross <mgross@linux.intel.com>
To:     Greg KH <gregkh@linuxfoundation.org>
Cc:     mark gross <mgross@linux.intel.com>, markgross@kernel.org,
        arnd@arndb.de, bp@suse.de, damien.lemoal@wdc.com,
        dragan.cvetic@xilinx.com, corbet@lwn.net, leonard.crestez@nxp.com,
        palmerdabbelt@google.com, paul.walmsley@sifive.com,
        peng.fan@nxp.com, robh+dt@kernel.org, shawnguo@kernel.org,
        linux-kernel@vger.kernel.org,
        Daniele Alessandrelli <daniele.alessandrelli@intel.com>,
        sundar.iyer@intel.com
Subject: Re: [PATCH 03/22] keembay-ipc: Add Keem Bay IPC module
Message-ID: <20201205033517.GA49179@linux.intel.com>
Reply-To: mgross@linux.intel.com
References: <20201201223511.65542-1-mgross@linux.intel.com>
 <20201201223511.65542-4-mgross@linux.intel.com>
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 <20201202174200.GG63356@mtg-dev.jf.intel.com>
 <X8fkflUXwSTGAoyQ@kroah.com>
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On Wed, Dec 02, 2020 at 08:01:18PM +0100, Greg KH wrote:
> On Wed, Dec 02, 2020 at 09:42:00AM -0800, mark gross wrote:
> > On Wed, Dec 02, 2020 at 07:16:20AM +0100, Greg KH wrote:
> > > On Tue, Dec 01, 2020 at 02:34:52PM -0800, mgross@linux.intel.com wrote:
> > > > --- a/MAINTAINERS
> > > > +++ b/MAINTAINERS
> > > > @@ -8955,6 +8955,14 @@ M:	Deepak Saxena <dsaxena@plexity.net>
> > > >  S:	Maintained
> > > >  F:	drivers/char/hw_random/ixp4xx-rng.c
> > > >  
> > > > +INTEL KEEM BAY IPC DRIVER
> > > > +M:	Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> > > > +M:	Mark Gross <mgross@linux.intel.com>
> > > > +S:	Maintained
> > > > +F:	Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml
> > > > +F:	drivers/soc/intel/keembay-ipc.c
> > > > +F:	include/linux/soc/intel/keembay-ipc.h
> > > 
> > > Sad that Intel is not going to actually pay you all to do this
> > > maintenance work for a brand new subsystem you are wanting to add to the
> > > tree :(
> > I thought adding my name to these maintainer items would help with continuity
> > as the individual engineers tend to move on to other things over time.
> > 
> > While I'm paid for a number of things at intel this is one of them.  My role is
> > as stable as I choose it to be at the point I'm at in my Intel career and the
> > business unit I'm now part of.  We can leave my name off if that would be
> > better.
> > 
> > Even if I'm not a VPU IP domain expert like Daniele is I can still chase down
> > the experts as needed after Daniele grows into other things over time.
> 
> I'm not objecting to your, or anyone else's name on this at all.  I'm
> just asking about Intel's support for this new codebase being added.
> Having a new subsystem from a major company and not have someone paid to
> actually maintain it seems really odd to me.
> 
> That's all.  If that's Intel's stance, that's fine, just wanted to
> clarify it is correct as I know some people at Intel have been confused
> recently about just what the S: field means.
I've been following up on whether the status field should be "Supported" or
"Maintained" at this time.  For this current instantiation of the VPU enabling
under review here I think Maintained most appropriate.  There are a good number
of people who look after it.

However; I have learned that the instantiations of the VPU after keem bay and
its follow on SoC will include an evolution of this stack and between now and
when those get close to landing that evolved version will become "Supported".

Given this, would it be more appropriate to put this stack into staging for a
while?

--mark