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([2a01:e34:ed2f:f020:8165:c1cc:d736:b53f]) by smtp.googlemail.com with ESMTPSA id h20sm7581744wmb.29.2020.12.05.10.30.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 05 Dec 2020 10:30:21 -0800 (PST) Subject: Re: [PATCH v3 2/2] clocksource: arm_arch_timer: Correct fault programming of CNTKCTL_EL1.EVNTI To: Marc Zyngier Cc: Keqian Zhu , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Thomas Gleixner , Catalin Marinas , Will Deacon , James Morse , Suzuki K Poulose , Sean Christopherson , Julien Thierry , Mark Brown , Andrew Morton , Alexios Zavras , wanghaibin.wang@huawei.com References: <20201204073126.6920-1-zhukeqian1@huawei.com> <20201204073126.6920-3-zhukeqian1@huawei.com> From: Daniel Lezcano Message-ID: <1ff86943-3f58-b57c-b3db-c3a92af79d2b@linaro.org> Date: Sat, 5 Dec 2020 19:30:20 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, On 05/12/2020 19:22, Marc Zyngier wrote: > Hi Daniel, > > On 2020-12-05 11:15, Daniel Lezcano wrote: >> Hi Marc, >> >> are you fine with this patch ? > > I am, although there still isn't any justification for the pos/lsb > rework in the commit message (and calling that variable lsb is somewhat > confusing). If you are going to apply it, please consider adding > the additional comment below. Ok, I will do that. Thanks for the additional comment -- Daniel >> On 04/12/2020 08:31, Keqian Zhu wrote: >>> ARM virtual counter supports event stream, it can only trigger an event >>> when the trigger bit (the value of CNTKCTL_EL1.EVNTI) of CNTVCT_EL0 >>> changes, >>> so the actual period of event stream is 2^(cntkctl_evnti + 1). For >>> example, >>> when the trigger bit is 0, then virtual counter trigger an event for >>> every >>> two cycles. > > "While we're at it, rework the way we compute the trigger bit position by >  making it more obvious that when bits [n:n-1] are both set (with n being >  the most significant bit), we pick bit (n + 1)." > > With that: > > Acked-by: Marc Zyngier > > Thanks, > >         M. -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog