Received: by 2002:a05:6a10:f347:0:0:0:0 with SMTP id d7csp1352288pxu; Sat, 5 Dec 2020 12:47:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJwtZzYobL/pPAi9CIwuD6VmazUfq8sPt/dCedhm20Fn3xX1D8XFEIqrxw2KK/c/iHE+Z1Zk X-Received: by 2002:a17:907:20a4:: with SMTP id pw4mr12572107ejb.499.1607201265459; Sat, 05 Dec 2020 12:47:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607201265; cv=none; d=google.com; s=arc-20160816; b=KTpPxOesPG4clze+cIZZNt1kOWW8OZ79EkzE1kJtNmf+Ba77w/CMqZZt8HbJpP3KbT vjPRTMLWiTVX2ekFC9L64NCAhmWjwuwP3D9mdC0gTprZHbZq3vIVAdpFDj/n3nZCgS74 djEcX4ozVbKzYCAhW/gBLqoJf6jYBB7n4DAcvOa2wUfm+pEEUg7sfc44ZFlDpD4sLkOF rHGJViBF+tcpJv/RfvhI/ZO/e3xD1kJ0jJJG/Uyih484YQl17JUKDFQ6IXjcQwHs+Mel 7Put7EQI1Hk4kCJEFYF62+ORkpkscI+ey1e9duVQQ3+YUYMsHEvRxnCGqaL/BUIUYBBa q9eA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=KgnaBBt5ABrDcm9nHWq/bn7n7+KFephyCfs7ChcR49k=; b=U1cfXBURexCa19mHRv4df2DRjZzfo7L3p2JEgxDcD0X4iXhLET1j7cxsc4zPiusQue dkyaxrq2pGy1w7b4XA8b1E5cRMqsvz/1du/rLhp22gPFQyv/8I6+wB3Ovtv72m1OWqC1 7wBYrykJtQs2zqjHdIhF5QlbI6HL4vbfmUgEAzdhW3lfaEu13z2YsY25fH/lH0eyGDPy mgOR5w/TkHZd7uzptFC1Iw386tSVJSfpuuWucnvW7cVU2p8xOyO03bQYGr1M4STw1K2f z3SfY6tclD6ETAQLongps/VLjydNuI0wFZKOUQLMK8Vp6Sx+8EF03ZPotYev65Q8qfpi TgiQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y23si3874152ejc.508.2020.12.05.12.47.22; Sat, 05 Dec 2020 12:47:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727099AbgLEUnp (ORCPT + 99 others); Sat, 5 Dec 2020 15:43:45 -0500 Received: from jabberwock.ucw.cz ([46.255.230.98]:37066 "EHLO jabberwock.ucw.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725996AbgLEUno (ORCPT ); Sat, 5 Dec 2020 15:43:44 -0500 Received: by jabberwock.ucw.cz (Postfix, from userid 1017) id C4F971C0B8B; Sat, 5 Dec 2020 21:43:01 +0100 (CET) Date: Sat, 5 Dec 2020 21:43:01 +0100 From: Pavel Machek To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Catalin Marinas , Marc Zyngier , Greg Kroah-Hartman , Peter Zijlstra , Morten Rasmussen , Qais Yousef , Suren Baghdasaryan , Quentin Perret , Tejun Heo , Li Zefan , Johannes Weiner , Ingo Molnar , Juri Lelli , Vincent Guittot , kernel-team@android.com Subject: Re: [PATCH v4 00/14] An alternative series for asymmetric AArch32 systems Message-ID: <20201205204301.GB8578@amd> References: <20201124155039.13804-1-will@kernel.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="kXdP64Ggrk/fb43R" Content-Disposition: inline In-Reply-To: <20201124155039.13804-1-will@kernel.org> User-Agent: Mutt/1.5.23 (2014-03-12) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --kXdP64Ggrk/fb43R Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue 2020-11-24 15:50:25, Will Deacon wrote: > Hello folks, >=20 > Here's version four of the wonderful patches I previously posted here: >=20 > v1: https://lore.kernel.org/r/20201027215118.27003-1-will@kernel.org > v2: https://lore.kernel.org/r/20201109213023.15092-1-will@kernel.org > v3: https://lore.kernel.org/r/20201113093720.21106-1-will@kernel.org >=20 > and which started life as a reimplementation of some patches from Qais: >=20 > https://lore.kernel.org/r/20201021104611.2744565-1-qais.yousef@arm.com >=20 > The aim of this series is to allow 32-bit ARM applications to run on > arm64 SoCs where not all of the CPUs support the 32-bit instruction set. > Unfortunately, such SoCs are real and will continue to be productised > over the next few years at least. Out of curiosity, what systems are that? Is the 32-bit available on the big or on the little cores? And... fun way to accelerate demise of arm32 :-). Best regards, Pavel --=20 http://www.livejournal.com/~pavelmachek --kXdP64Ggrk/fb43R Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEARECAAYFAl/L8NUACgkQMOfwapXb+vJKawCgoM+JfmKVtgscUMb1upqBcin4 lTMAn1VlyMbbfJqa4BTWIYugvngHmIor =yYfr -----END PGP SIGNATURE----- --kXdP64Ggrk/fb43R--