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From:   Ard Biesheuvel <ardb@kernel.org>
Date:   Mon, 7 Dec 2020 10:49:26 +0100
Message-ID: <CAMj1kXFdtom+OBJ84he9C5eNw-KJ8zwW04WB0ab6Gp_DCiYkRg@mail.gmail.com>
Subject: Re: [PATCH] arm64: mm: decrease the section size to reduce the memory
 reserved for the page map
To:     Mike Rapoport <rppt@linux.ibm.com>
Cc:     Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>,
        Wei Li <liwei213@huawei.com>,
        Barry Song <song.bao.hua@hisilicon.com>,
        Steve Capper <steve.capper@arm.com>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        fengbaopeng2@hisilicon.com, butao@hisilicon.com,
        Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>
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Precedence: bulk

On Mon, 7 Dec 2020 at 10:42, Mike Rapoport <rppt@linux.ibm.com> wrote:
>
> On Mon, Dec 07, 2020 at 09:35:06AM +0000, Marc Zyngier wrote:
> > On 2020-12-07 09:09, Ard Biesheuvel wrote:
> > > (+ Marc)
> > >
> > > On Fri, 4 Dec 2020 at 12:14, Will Deacon <will@kernel.org> wrote:
> > > >
> > > > On Fri, Dec 04, 2020 at 09:44:43AM +0800, Wei Li wrote:
> > > > > For the memory hole, sparse memory model that define SPARSEMEM_VMEMMAP
> > > > > do not free the reserved memory for the page map, decrease the section
> > > > > size can reduce the waste of reserved memory.
> > > > >
> > > > > Signed-off-by: Wei Li <liwei213@huawei.com>
> > > > > Signed-off-by: Baopeng Feng <fengbaopeng2@hisilicon.com>
> > > > > Signed-off-by: Xia Qing <saberlily.xia@hisilicon.com>
> > > > > ---
> > > > >  arch/arm64/include/asm/sparsemem.h | 2 +-
> > > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/arch/arm64/include/asm/sparsemem.h b/arch/arm64/include/asm/sparsemem.h
> > > > > index 1f43fcc79738..8963bd3def28 100644
> > > > > --- a/arch/arm64/include/asm/sparsemem.h
> > > > > +++ b/arch/arm64/include/asm/sparsemem.h
> > > > > @@ -7,7 +7,7 @@
> > > > >
> > > > >  #ifdef CONFIG_SPARSEMEM
> > > > >  #define MAX_PHYSMEM_BITS     CONFIG_ARM64_PA_BITS
> > > > > -#define SECTION_SIZE_BITS    30
> > > > > +#define SECTION_SIZE_BITS    27
> > > >
> > > > We chose '30' to avoid running out of bits in the page flags. What
> > > > changed?
> > > >
> > > > With this patch, I can trigger:
> > > >
> > > > ./include/linux/mmzone.h:1170:2: error: Allocator MAX_ORDER exceeds
> > > > SECTION_SIZE
> > > > #error Allocator MAX_ORDER exceeds SECTION_SIZE
> > > >
> > > > if I bump up NR_CPUS and NODES_SHIFT.
> > > >
> > >
> > > Does this mean we will run into problems with the GICv3 ITS LPI tables
> > > again if we are forced to reduce MAX_ORDER to fit inside
> > > SECTION_SIZE_BITS?
> >
> > Most probably. We are already massively constraint on platforms
> > such as TX1, and dividing the max allocatable range by 8 isn't
> > going to make it work any better...
>
> I don't think MAX_ORDER should shrink. Even if SECTION_SIZE_BITS is
> reduced it should accomodate the existing MAX_ORDER.
>
> My two pennies.
>

But include/linux/mmzone.h:1170 has this:

#if (MAX_ORDER - 1 + PAGE_SHIFT) > SECTION_SIZE_BITS
#error Allocator MAX_ORDER exceeds SECTION_SIZE
#endif

and Will managed to trigger it after applying this patch.