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Date:   Mon, 7 Dec 2020 11:02:06 -0600
From:   Rob Herring <robh@kernel.org>
To:     Liu Ying <victor.liu@nxp.com>
Cc:     linux-arm-kernel@lists.infradead.org,
        dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, p.zabel@pengutronix.de,
        airlied@linux.ie, daniel@ffwll.ch, shawnguo@kernel.org,
        s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
        linux-imx@nxp.com, maarten.lankhorst@linux.intel.com,
        mripard@kernel.org, tzimmermann@suse.de,
        laurentiu.palcu@oss.nxp.com
Subject: Re: [PATCH v3 3/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPR
 channel binding
Message-ID: <20201207170206.GA434964@robh.at.kernel.org>
References: <1607311260-13983-1-git-send-email-victor.liu@nxp.com>
 <1607311260-13983-4-git-send-email-victor.liu@nxp.com>
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On Mon, Dec 07, 2020 at 11:20:57AM +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel.
> 
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> Note that this depends on the 'two cell binding' clock patch set which has
> already landed in Shawn's i.MX clk/imx git branch.  Otherwise, imx8-lpcg.h
> won't be found.
> 
> v2->v3:
> * No change.
> 
> v1->v2:
> * Use new dt binding way to add clocks in the example.
> 
>  .../bindings/display/imx/fsl,imx8qxp-dprc.yaml     | 87 ++++++++++++++++++++++
>  1 file changed, 87 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
> new file mode 100644
> index 00000000..91e9472
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
> @@ -0,0 +1,87 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dprc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8qm/qxp Display Prefetch Resolve Channel
> +
> +maintainers:
> +  - Liu Ying <victor.liu@nxp.com>
> +
> +description: |
> +  The i.MX8qm/qxp Display Prefetch Resolve Channel(DPRC) is an engine which
> +  fetches display data before the display pipeline needs the data to drive
> +  pixels in the active display region.  This data is transformed, or resolved,
> +  from a variety of tiled buffer formats into linear format, if needed.
> +  The DPR works with a double bank memory structure.  This memory structure is
> +  implemented in the Resolve Tile Memory(RTRAM) and the banks are referred to
> +  as A and B.  Each bank is either 4 or 8 lines high depending on the source
> +  frame buffer format.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - const: fsl,imx8qxp-dpr-channel
> +      - const: fsl,imx8qm-dpr-channel

enum instead of oneOf+const.

With that,

Reviewed-by: Rob Herring <robh@kernel.org>

> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: apb clock
> +      - description: b clock
> +      - description: rtram clock
> +
> +  clock-names:
> +    items:
> +      - const: apb
> +      - const: b
> +      - const: rtram
> +
> +  fsl,sc-resource:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: The SCU resource ID associated with this DPRC instance.
> +
> +  fsl,prgs:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    description: |
> +      List of phandle which points to Prefetch Resolve Gaskets(PRGs)
> +      associated with this DPRC instance.
> +
> +  power-domains:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - fsl,sc-resource
> +  - fsl,prgs
> +  - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/imx8-lpcg.h>
> +    #include <dt-bindings/firmware/imx/rsrc.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    dpr-channel@56100000 {
> +        compatible = "fsl,imx8qxp-dpr-channel";
> +        reg = <0x56100000 0x10000>;
> +        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&dc0_dpr1_lpcg IMX_LPCG_CLK_4>,
> +                 <&dc0_dpr1_lpcg IMX_LPCG_CLK_5>,
> +                 <&dc0_rtram1_lpcg IMX_LPCG_CLK_0>;
> +        clock-names = "apb", "b", "rtram";
> +        fsl,sc-resource = <IMX_SC_R_DC_0_VIDEO0>;
> +        fsl,prgs = <&dc0_prg4>, <&dc0_prg5>;
> +        power-domains = <&pd IMX_SC_R_DC_0>;
> +    };
> -- 
> 2.7.4
>