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Tue, 8 Dec 2020 09:48:06 +0000 Message-ID: <24222c64cbc9ceb1d3a48a8ed5fa74a32d9e5eee.camel@nxp.com> Subject: Re: [PATCH 3/4] dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp From: Liu Ying To: Guido =?ISO-8859-1?Q?G=FCnther?= Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org, a.hajda@samsung.com, narmstrong@baylibre.com, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@siol.net, airlied@linux.ie, daniel@ffwll.ch, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, robert.chiras@nxp.com, martin.kepplinger@puri.sm Date: Tue, 08 Dec 2020 17:46:16 +0800 In-Reply-To: <20201208090710.GC20575@bogon.m.sigxcpu.org> References: <1607067224-15616-1-git-send-email-victor.liu@nxp.com> <1607067224-15616-4-git-send-email-victor.liu@nxp.com> <20201208090710.GC20575@bogon.m.sigxcpu.org> Content-Type: text/plain; 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Could you look into converting to YAML before adding more > values? Yes, a YAML one would be good. I'll try to do the conversion and then add the binding support for the i.MX8qxp Mixel combo PHY in it. Liu Ying > Cheers, > -- Guido > > On Fri, Dec 04, 2020 at 03:33:43PM +0800, Liu Ying wrote: > > Add support for Mixel MIPI DPHY + LVDS PHY combo IP > > as found on Freescale i.MX8qxp SoC. > > > > Cc: Guido Günther > > Cc: Kishon Vijay Abraham I > > Cc: Vinod Koul > > Cc: Rob Herring > > Cc: NXP Linux Team > > Signed-off-by: Liu Ying > > --- > > Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 8 +++++++- > > 1 file changed, 7 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt > > index 9b23407..0afce99 100644 > > --- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt > > +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt > > @@ -4,9 +4,13 @@ The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the > > MIPI-DSI IP from Northwest Logic). It represents the physical layer for the > > electrical signals for DSI. > > > > +The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work > > +in either MIPI-DSI PHY mode or LVDS PHY mode. > > + > > Required properties: > > -- compatible: Must be: > > +- compatible: Should be one of: > > - "fsl,imx8mq-mipi-dphy" > > + - "fsl,imx8qxp-mipi-dphy" > > - clocks: Must contain an entry for each entry in clock-names. > > - clock-names: Must contain the following entries: > > - "phy_ref": phandle and specifier referring to the DPHY ref clock > > @@ -14,6 +18,8 @@ Required properties: > > - #phy-cells: number of cells in PHY, as defined in > > Documentation/devicetree/bindings/phy/phy-bindings.txt > > this must be <0> > > +- fsl,syscon: Phandle to a system controller, as required by the PHY > > + in i.MX8qxp SoC. > > > > Optional properties: > > - power-domains: phandle to power domain > > -- > > 2.7.4 > >