Received: by 2002:a05:6a10:f347:0:0:0:0 with SMTP id d7csp3172941pxu; Tue, 8 Dec 2020 05:33:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJyUaPuQU/w9bQ1ovwu7zaJcmKcFbYypMYCNv1UGSN+lnHOej/kZzO4MHyMuHqJJHO2rxCx7 X-Received: by 2002:aa7:c3cf:: with SMTP id l15mr14992727edr.282.1607434433231; Tue, 08 Dec 2020 05:33:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607434433; cv=none; d=google.com; s=arc-20160816; b=H9FAHFGHWH14aMeqrOUeEChz3HY4artc7cPQqIOOXcJClHIaC4pkyz+qfuR0T8YnNC Q7txjMjqQ7CDybi8SoaHYGP5Fw1TA7aOt3r38HDe8wPv2vo7r59UaaeoszPkD3rKaMtr PS5l/tHjKi4hpx9QmXtKW++gpwQ573jTVU/AV2E7kpppAfg9MtdoFNU8HmUZtcWC1YzG Vo2O6pzDxSliTyq8+5OJrP0WH2gL51J1VJur2RMr7+SGqj498K4dtaeWx68OzqEz9zuN QI1nU+899Qwx0N9PLyGXDZNwZSv3/9ra8R4pYZGOCdTEQ4Zb6kU1nCAt13hZuVw3HKN8 cARA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ttXuAFfh0yP02hc85lO4Amhpq9uaEoKPioNTk3Ypzv4=; b=qG3q/lZQhQFrPbix50mWTrnUkKeqC0f1GQCRFA4YWpocYgZZKi8lYfp72CJCf1OVuU e6TSZMESg5iTw78xLvfPFvwSVeagWfBNudpsItsMzotiNpJd4pgz0edVKud2Vmz5J9WR j/vI1h+Co91d4Hrc4On78k+rJoNT4abETObhBTI+sZCpi7TUkRejODtqE2lI95jxeDkJ 7NKq0jowy2g/XpIrNsdHWsxx5r+DC5mMc+4Mp+iRj3o3nn1ypJV74Y3uoCRbQe8Mtv8n fL3BpGB4caH6EjFctrX9MCkFKkSilgfSY5Iy0nBOMufrJz5aYW7NWv1VGf4PIuCls3jw Y9zg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id s20si8113592ejb.155.2020.12.08.05.33.30; Tue, 08 Dec 2020 05:33:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729483AbgLHNaV (ORCPT + 99 others); Tue, 8 Dec 2020 08:30:21 -0500 Received: from mail.kernel.org ([198.145.29.99]:49580 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726080AbgLHNaT (ORCPT ); Tue, 8 Dec 2020 08:30:19 -0500 From: Will Deacon Authentication-Results: mail.kernel.org; dkim=permerror (bad message/signature format) To: linux-arm-kernel@lists.infradead.org Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Will Deacon , Catalin Marinas , Marc Zyngier , Greg Kroah-Hartman , Peter Zijlstra , Morten Rasmussen , Qais Yousef , Suren Baghdasaryan , Quentin Perret , Tejun Heo , Li Zefan , Johannes Weiner , Ingo Molnar , Juri Lelli , Vincent Guittot , kernel-team@android.com Subject: [PATCH v5 11/15] arm64: Implement task_cpu_possible_mask() Date: Tue, 8 Dec 2020 13:28:31 +0000 Message-Id: <20201208132835.6151-12-will@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201208132835.6151-1-will@kernel.org> References: <20201208132835.6151-1-will@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Provide an implementation of task_cpu_possible_mask() so that we can prevent 64-bit-only cores being added to the 'cpus_mask' for compat tasks on systems with mismatched 32-bit support at EL0, Signed-off-by: Will Deacon --- arch/arm64/include/asm/mmu_context.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index 0672236e1aea..a5c917fa49aa 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -251,6 +251,19 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, #define deactivate_mm(tsk,mm) do { } while (0) #define activate_mm(prev,next) switch_mm(prev, next, current) +static inline const struct cpumask * +task_cpu_possible_mask(struct task_struct *p) +{ + if (!static_branch_unlikely(&arm64_mismatched_32bit_el0)) + return cpu_possible_mask; + + if (!is_compat_thread(task_thread_info(p))) + return cpu_possible_mask; + + return system_32bit_el0_cpumask(); +} +#define task_cpu_possible_mask task_cpu_possible_mask + void verify_cpu_asid_bits(void); void post_ttbr_update_workaround(void); -- 2.29.2.576.ga3fc446d84-goog