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From:   Yash Shah <yash.shah@openfive.com>
To:     Rob Herring <robh@kernel.org>
CC:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "bp@suse.de" <bp@suse.de>,
        "anup@brainfault.org" <anup@brainfault.org>,
        "Jonathan.Cameron@huawei.com" <Jonathan.Cameron@huawei.com>,
        "wsa@kernel.org" <wsa@kernel.org>,
        "sam@ravnborg.org" <sam@ravnborg.org>,
        "aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
        "palmer@dabbelt.com" <palmer@dabbelt.com>,
        "Paul Walmsley ( Sifive)" <paul.walmsley@sifive.com>,
        Sagar Kadam <sagar.kadam@openfive.com>,
        Sachin Ghadi <sachin.ghadi@openfive.com>
Subject: RE: [PATCH v2 1/2] RISC-V: Update l2 cache DT documentation to add
 support for SiFive FU740
Thread-Topic: [PATCH v2 1/2] RISC-V: Update l2 cache DT documentation to add
 support for SiFive FU740
Thread-Index: AQHWxtu9bQuNh+qvKEyj5EgsQbzkSant5A2AgABWksA=
Date:   Wed, 9 Dec 2020 05:06:01 +0000
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References: <1606714984-16593-1-git-send-email-yash.shah@sifive.com>
 <20201208232141.GA3292265@robh.at.kernel.org>
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> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 09 December 2020 04:52
> To: Yash Shah <yash.shah@openfive.com>
> Cc: linux-kernel@vger.kernel.org; linux-riscv@lists.infradead.org;
> devicetree@vger.kernel.org; bp@suse.de; anup@brainfault.org;
> Jonathan.Cameron@huawei.com; wsa@kernel.org; sam@ravnborg.org;
> aou@eecs.berkeley.edu; palmer@dabbelt.com; Paul Walmsley ( Sifive)
> <paul.walmsley@sifive.com>; Sagar Kadam <sagar.kadam@openfive.com>;
> Sachin Ghadi <sachin.ghadi@openfive.com>
> Subject: Re: [PATCH v2 1/2] RISC-V: Update l2 cache DT documentation to
> add support for SiFive FU740
>=20
> [External Email] Do not click links or attachments unless you recognize t=
he
> sender and know the content is safe
>=20
> On Mon, Nov 30, 2020 at 11:13:03AM +0530, Yash Shah wrote:
> > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
> > compared to 3 in FU540. Update the DT documentation accordingly with
> > "compatible" and "interrupt" property changes.
>=20
> 'dt-bindings: riscv: ...' for the subject.
>=20
> >
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> > ---
> > Changes in v2:
> > - Changes as per Rob Herring's request on v1
> > ---
> >  .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 35
> > ++++++++++++++++++++--
> >  1 file changed, 32 insertions(+), 3 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > index efc0198..749265c 100644
> > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > @@ -27,6 +27,7 @@ select:
> >        items:
> >          - enum:
> >              - sifive,fu540-c000-ccache
> > +            - sifive,fu740-c000-ccache
> >
> >    required:
> >      - compatible
> > @@ -34,7 +35,9 @@ select:
> >  properties:
> >    compatible:
> >      items:
> > -      - const: sifive,fu540-c000-ccache
> > +      - enum:
> > +          - sifive,fu540-c000-ccache
> > +          - sifive,fu740-c000-ccache
> >        - const: cache
> >
> >    cache-block-size:
> > @@ -53,9 +56,15 @@ properties:
> >
> >    interrupts:
> >      description: |
> > -      Must contain entries for DirError, DataError and DataFail signal=
s.
> > +      Must contain 3 entries for FU540 (DirError, DataError and DataFa=
il) or
> 4
> > +      entries for other chips (DirError, DirFail, DataError, DataFail
> > + signals)
>=20
> While below is wrong, don't give descriptions that just repeat what the
> schema says.

Ok will remove the above description.

>=20
> >      minItems: 3
> > -    maxItems: 3
> > +    maxItems: 4
> > +    items:
> > +      - description: DirError interrupt
> > +      - description: DirFail interrupt
> > +      - description: DataError interrupt
> > +      - description: DataFail interrupt
>=20
> This says DataFail is optional.

I will move back to your initial suggestion to add the new entry "DirFail" =
as the last index to keep the order same.
Will make the corresponding changes in the driver and send a v3 patch.

Thanks for your review.

- Yash