Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
IronPort-SDR: pjd57PINjurwEY6w+ve5EXW3sJ56RR2Y3cUkOPllhn1HSfO+QFjkukcDT/rRqfLf0WJHPNRxz4
 RvWYhJ1uUW4RSy1ogmEBUbYpElnSXGzKd/ria+fPqBY0NvSK7g+Nr1SByJeK2wQ03F9B8IBpdd
 k+RNEXC5QiZAWbD1mGdQcEFuXmT+ZFwPTC4uTSy18A16zn69PZbgU3UE56zsyeQyfqYiGBv6Yc
 3Z+5Gu8wSnFow7r9ZSmTRu8/eU2FFZGczPtOM6KiGqXnHid0QWE8zwhvNBM7pu34M2QwE46bfy
 hBQ=
From:   Lars Povlsen <lars.povlsen@microchip.com>
To:     Linus Walleij <linus.walleij@linaro.org>,
        Rob Herring <robh@kernel.org>
CC:     Lars Povlsen <lars.povlsen@microchip.com>,
        Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
        <devicetree@vger.kernel.org>, <linux-gpio@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>,
        Alexandre Belloni <alexandre.belloni@bootlin.com>
Subject: [PATCH -next 2/3] dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support
Date:   Wed, 9 Dec 2020 15:27:52 +0100
Message-ID: <20201209142753.683208-3-lars.povlsen@microchip.com>
In-Reply-To: <20201209142753.683208-1-lars.povlsen@microchip.com>
References: <20201209142753.683208-1-lars.povlsen@microchip.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
Precedence: bulk

This describe the new bindings for the added IRQ support in the
pinctrl-microchip-sgpio driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
 .../bindings/pinctrl/microchip,sparx5-sgpio.yaml | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
index 08325bf77a81..df0c83cb1c6e 100644
--- a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
@@ -91,6 +91,18 @@ patternProperties:
          controlled indirectly by the "ngpios" property: (ngpios/32).
         const: 3
 
+      interrupts:
+        description: Specifies the sgpio IRQ (in parent controller)
+        maxItems: 1
+
+      interrupt-controller: true
+
+      '#interrupt-cells':
+        description:
+         Specifies the pin (port and bit) and flags, as defined in
+         defined in include/dt-bindings/interrupt-controller/irq.h
+        const: 3
+
       ngpios:
         description: The numbers of GPIO's exposed. This must be a
           multiple of 32.
@@ -118,6 +130,7 @@ required:
 
 examples:
   - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
     sgpio2: gpio@1101059c {
       #address-cells = <1>;
       #size-cells = <0>;
@@ -134,6 +147,9 @@ examples:
         gpio-controller;
         #gpio-cells = <3>;
         ngpios = <96>;
+        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-controller;
+        #interrupt-cells = <3>;
       };
       sgpio_out2: gpio@1 {
         compatible = "microchip,sparx5-sgpio-bank";
-- 
2.25.1