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Date:   Wed, 9 Dec 2020 14:16:27 -0600
From:   Rob Herring <robh@kernel.org>
To:     Sowjanya Komatineni <skomatineni@nvidia.com>
Cc:     jonathanh@nvidia.com, bparrot@ti.com, hverkuil@xs4all.nl,
        mchehab@kernel.org, linux-media@vger.kernel.org,
        devicetree@vger.kernel.org, thierry.reding@gmail.com,
        linux-tegra@vger.kernel.org, sakari.ailus@iki.fi,
        robh+dt@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 11/13] dt-bindings: tegra: Update csi data-lanes to
 maximum 8 lanes
Message-ID: <20201209201627.GA868687@robh.at.kernel.org>
References: <1607022002-26575-1-git-send-email-skomatineni@nvidia.com>
 <1607022002-26575-12-git-send-email-skomatineni@nvidia.com>
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On Thu, 03 Dec 2020 11:00:00 -0800, Sowjanya Komatineni wrote:
> Tegra VI/CSI hardware don't have native 8 lane CSI RX port.
> 
> But x8 capture can be supported by using consecutive x4 ports
> simultaneously with HDMI-to-CSI bridges where source image is split
> on to two x4 ports.
> 
> This patch updates dt-bindings for csi endpoint data-lane property
> with maximum of 8 lanes.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  .../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt       | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

Acked-by: Rob Herring <robh@kernel.org>