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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id t19sm753901otp.36.2020.12.09.15.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Dec 2020 15:30:13 -0800 (PST) Received: (nullmailer pid 1281044 invoked by uid 1000); Wed, 09 Dec 2020 23:30:11 -0000 Date: Wed, 9 Dec 2020 17:30:11 -0600 From: Rob Herring To: Atish Patra Cc: linux-kernel@vger.kernel.org, Albert Ou , Alistair Francis , Anup Patel , Bin Meng , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Ivan.Griffin@microchip.com, Cyril.Jean@microchip.com, Daire McNamara , Conor.Dooley@microchip.com Subject: Re: [PATCH v3 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Message-ID: <20201209233011.GA1276461@robh.at.kernel.org> References: <20201204085835.2406541-1-atish.patra@wdc.com> <20201204085835.2406541-3-atish.patra@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201204085835.2406541-3-atish.patra@wdc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Dec 04, 2020 at 12:58:32AM -0800, Atish Patra wrote: > Add YAML DT binding documentation for the Microchip PolarFire SoC. > It is documented at: > > https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide > > Signed-off-by: Atish Patra > --- > .../devicetree/bindings/riscv/microchip.yaml | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml > > diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml > new file mode 100644 > index 000000000000..66e63c2bf359 > --- /dev/null > +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml > @@ -0,0 +1,28 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR MIT) See what checkpatch.pl says. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/riscv/microchip.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip PolarFire SoC-based boards device tree bindings > + > +maintainers: > + - Cyril Jean > + - Lewis Hanly > + > +description: > + Microchip PolarFire SoC-based boards > + > +properties: > + $nodename: > + const: '/' > + compatible: > + items: > + - enum: > + - microchip,mpfs-icicle-kit > + - const: microchip,polarfire-soc > + - const: microchip,mpfs Is this last compatible really useful? Usually better to just have SoC and board (or SoM plus baseboard) compatibles. Rob