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From:   Yash Shah <yash.shah@sifive.com>
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        Yash Shah <yash.shah@sifive.com>
Subject: [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC
Date:   Thu, 10 Dec 2020 15:58:01 +0530
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Add support for additional interrupt present in SiFive FU740 chip.

Changes:
v3:
- Rename the subject line of dt-binding patch
- Add the additional interrupt "DirFail" as the last entry so as to keep
  the order of all previous index same.

v2:
- Changes as per Rob Herring's request on v1

Yash Shah (2):
  dt-bindings: riscv: Update l2 cache DT documentation to add support
    for SiFive FU740
  RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive
    FU740

 .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++---
 drivers/soc/sifive/sifive_l2_cache.c               | 27 +++++++++++++++--
 2 files changed, 54 insertions(+), 7 deletions(-)

-- 
2.7.4