Message-ID: <44F8563B.3050505@shadowen.org>
Date: Fri, 01 Sep 2006 16:48:11 +0100
From: Andy Whitcroft <apw@shadowen.org>
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To: schwidefsky@de.ibm.com
CC: Dave Hansen <haveblue@us.ibm.com>, linux-kernel@vger.kernel.org,
       virtualization@lists.osdl.org, akpm@osdl.org, nickpiggin@yahoo.com.au,
       frankeh@watson.ibm.com, rhim@cc.gateh.edu
Subject: Re: [patch 3/9] Guest page hinting: volatile page cache.
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Martin Schwidefsky wrote:
> On Fri, 2006-09-01 at 07:57 -0700, Dave Hansen wrote:
>>> +#define PG_state_change                21      /* HV page state is changing. */
>>> +#define PG_discarded           22      /* HV page has been discarded. */ 
>> We're already desperately short on page flags on 32-bit architectures.
>> It seems a wee bit silly to add two arch-generic flags for what is a
>> very specialized arch-specific feature at this point.
> 
> There are even three additional page flags if you apply the full set of
> patches.
> 
>> I know that there are 32-bit s390 kernels, but would this be a
>> reasonable feature to restrict to only 64-bit kernels?  That might be a
>> decent compromise.
> 
> Yes, it is definitly an option to make this a 64-bit only features. In
> particular because the ESSA instruction that is used on s390 is only
> available in zarch mode (=64 bit).

Wow.  Well there are only 7 extra bits available in 64 bit mode (the
FIELDS area is larger on 64bit machines).  Do we really, really need
three new bits.  What are they being used for here.

-apw
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