Received: by 2002:a05:6a10:f347:0:0:0:0 with SMTP id d7csp35188pxu; Thu, 10 Dec 2020 17:27:19 -0800 (PST) X-Google-Smtp-Source: ABdhPJwG6wr6lLVlAkJzLOld36B0Nh3ZINwJqarAOZx8PmhImgN8PAzV9tiiQGOor6jU+SN3uw0k X-Received: by 2002:a50:fd88:: with SMTP id o8mr9570188edt.386.1607650038740; Thu, 10 Dec 2020 17:27:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607650038; cv=none; d=google.com; s=arc-20160816; b=uvnug9ifxk8Y1V5ZrExfSTO7zR9w/gm07ckE/IK8HewzPGtpNXuT+RE5iNM3Iwtu7q 7Vd8qenYDGLd7OGHNQDAKZe/Ntn7gayXyjLl9zo5ExGr4T5RmJGllU7/wYRiYtSe17C6 siWd5XzCvswFTKYDLlwZtnjp3z4DvU13q2+oJnufjeAxjo0YDfJLv//NswqHykVgvRwy LAd6H2DZv7MOysizmCfHz7EzPznE8M++6uPmBqPgStTf8Tu5tvxMaUTXXd34lN/rDiWT 4rkUHM6G+8D49sffpQhHBvGvBAjkQbKaL7Vc4Gi95rbkJv+FG/ayhKINrNk4vbM1i7v9 Au5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=7gvh3enTyM7r16asGFsXp25EQVi9nM03JLF3FLpI4e8=; b=XMd4VR+z7Iudq/1SrbR+aJfyzDX6yV2i751S2vHwhGMtYEGgnOXqIU5V8Sid3GIZAY NamHxzDps0Z+k5byoL216FKpOFiGdZHpWWTegeYdiXbf+0Dy1cEGDA0jUI5ta0yZ1LkO kG/l70/3XUvnylsRzl7DlfCE0VLmgpVFNRRbjYofvMXShurkOUPKemF4RqJnqJYDcw5e 3ftnt9bgrJxnN4uuKCYVdPgo4H3AdzI2lVnP497qN+py/tacZPhUe3D5CEhRc+fFvVNa /LfsC5G8jmsxYoeOvmlMb3saVIYvuD7+s0aTImPrNK5BHf+Zjt2wbxs4ymkjUQsGbjdO j7OA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=g8KiW139; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j13si3629266edt.512.2020.12.10.17.26.56; Thu, 10 Dec 2020 17:27:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=g8KiW139; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388729AbgLJOWz (ORCPT + 99 others); Thu, 10 Dec 2020 09:22:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729076AbgLJOWy (ORCPT ); Thu, 10 Dec 2020 09:22:54 -0500 Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64352C0613CF; Thu, 10 Dec 2020 06:22:14 -0800 (PST) Received: by mail-pf1-x443.google.com with SMTP id s21so4192510pfu.13; Thu, 10 Dec 2020 06:22:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=7gvh3enTyM7r16asGFsXp25EQVi9nM03JLF3FLpI4e8=; b=g8KiW139pOV2susxo8HdW/YCjk7r0bCJ4v1VqLcaQGdS+kugolJyuTrKNLYE02M5Oy hwO0pFh3VRMHS9xsoL4zKAssx6DcQGdsUPQWjDb8Ms2QdI/RaFjWvBMAs3LlajEYLm7B E/A2Nm7BKrKcghKE4sxxyC17d2pz3yJPxpj7vgNOtGlyOeLGfWzS+Yh+MQnFrYW4XKPv Et7xQ/S87ZeU5xl/3i8CHeYDwkhdvTgBFJG+CL1zBOYmJ35bV5D/W9PFODHWO9hTZGHF +ffG/RBD1oTr9lZrJf6/aM81EXYASfnDpjNY7jdq5a4j15se5zsQCeoNQNwtCZaeEsNH DC2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=7gvh3enTyM7r16asGFsXp25EQVi9nM03JLF3FLpI4e8=; b=RxNOZ8c2DaW7OAjXAX4uI0VkrK2w73os6XVXydFmlRywHnvJLlXEGAKL7e8unjb/g5 1dE6LEZsIyjiQM44dxi6imrY0RyKRXnM5OA++HnrI0Z9IRCYahE6NTEBI45yB+xu85Vb 3qrCcDJ3DLwtSZW8QRF6YlfoVeYluMoIOs95oonsQ9GV+zRyA04+fA78NjCkGWXvIZ8n DeLlXDulxdHNGwf8l3R7v9xIv4zkMEZrZ7gy6ijhaXK/nMrW//IgtR6o3Rjv91uL2lWm 7Wo5qnbc/h5bYVoaMO9KlaxNieApy9mrFE1SXzOO8NKQQgPKfr4diQUR2447fCAPcLBi gOQg== X-Gm-Message-State: AOAM533/AF1mlq4+McGx7acs5oB96QqnR5CHy67AwLd3W0Iqj0AzXF3h IJOY8udV9/MmewAvBoxRP03yjADHdCPgsSxCToA= X-Received: by 2002:a63:4002:: with SMTP id n2mr6926113pga.4.1607610133882; Thu, 10 Dec 2020 06:22:13 -0800 (PST) MIME-Version: 1.0 References: <20201129110803.2461700-1-daniel@0x0f.com> <20201129110803.2461700-4-daniel@0x0f.com> In-Reply-To: <20201129110803.2461700-4-daniel@0x0f.com> From: Andy Shevchenko Date: Thu, 10 Dec 2020 16:23:02 +0200 Message-ID: Subject: Re: [PATCH v4 3/5] gpio: msc313: MStar MSC313 GPIO driver To: Daniel Palmer Cc: SoC Team , "open list:GPIO SUBSYSTEM" , devicetree , linux-arm Mailing List , Linux Kernel Mailing List , Linus Walleij , Rob Herring , Willy Tarreau Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Nov 29, 2020 at 1:10 PM Daniel Palmer wrote: > > This adds a driver that supports the GPIO block found in > MStar/SigmaStar ARMv7 SoCs. > > The controller seems to have enough register for 128 lines > but where they are wired up differs between chips and > no currently known chip uses anywhere near 128 lines so there > needs to be some per-chip data to collect together what lines > actually have physical pins attached and map the right names to them. > > The core peripherals seem to use the same lines on the > currently known chips but the lines used for the sensor > interface, lcd controller etc pins seem to be totally > different between the infinity and mercury chips > > The code tries to collect all of the re-usable names, > offsets etc together so that it's easy to build the extra > per-chip data for other chips in the future. > > So far this only supports the MSC313 and MSC313E chips. > > Support for the SSC8336N (mercury5) is trivial to add once > all of the lines have been mapped out. ... > +#include > +#include > +#include > +#include > +#include > +#include > +#include Perhaps ordered? ... > + /* > + * only the spi0 pins have interrupts on the parent > + * on all of the known chips and so far they are all > + * mapped to the same place > + */ You have a different comment style here (no capital letter, no period). > + if (offset >= OFF_SPI0_CZ && offset <= OFF_SPI0_DO) { Why not traditional pattern, i.e. if (...) return -EINVAL; ... ? > + *parent_type = child_type; > + *parent = ((offset - OFF_SPI0_CZ) >> 2) + 28; > + return 0; > + } > + > + return -EINVAL; ... > + ret = devm_gpiochip_add_data(dev, gpiochip, gpio); > + return ret; Purpose? return devm_...(...); ... > +static int msc313_gpio_remove(struct platform_device *pdev) > +{ > + return 0; > +} Purpose? ... > +static const struct of_device_id msc313_gpio_of_match[] = { > +#ifdef CONFIG_MACH_INFINITY What's the point? Are you expecting two drivers for the same IP? > + { > + .compatible = "mstar,msc313-gpio", > + .data = &msc313_data, > + }, > +#endif > + { } > +}; ... > +static struct platform_driver msc313_gpio_driver = { > + .driver = { > + .name = DRIVER_NAME, > + .of_match_table = msc313_gpio_of_match, > + .pm = &msc313_gpio_ops, > + }, > + .probe = msc313_gpio_probe, > + .remove = msc313_gpio_remove, > +}; > + Redundant blank line. > +builtin_platform_driver(msc313_gpio_driver); -- With Best Regards, Andy Shevchenko