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Subject: Re: [PATCH 6/9] ARM: dts: exynos: correct PMIC interrupt trigger
 level on Odroid XU3 family
To:     Krzysztof Kozlowski <krzk@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
        Lee Jones <lee.jones@linaro.org>,
        Chanwoo Choi <cw00.choi@samsung.com>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org
Cc:     Sylwester Nawrocki <snawrocki@kernel.org>
From:   Marek Szyprowski <m.szyprowski@samsung.com>
Message-ID: <351d77de-0756-ee16-535a-4ce0fbc2ba04@samsung.com>
Date:   Fri, 11 Dec 2020 16:49:32 +0100
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        <CGME20201210212931eucas1p2e43bfd1d65d130c0b4f00ea9210658f9@eucas1p2.samsung.com>
        <20201210212903.216728-6-krzk@kernel.org>
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On 10.12.2020 22:29, Krzysztof Kozlowski wrote:
> The Samsung PMIC datasheets describe the interrupt line as active low
> with a requirement of acknowledge from the CPU.  The falling edge
> interrupt will mostly work but it's not correct.
>
> Fixes: aac4e0615341 ("ARM: dts: odroidxu3: Enable wake alarm of S2MPS11 RTC")
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>   arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +-
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> index d0df560eb0db..6d690b1db099 100644
> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> @@ -509,7 +509,7 @@ pmic@66 {
>   		samsung,s2mps11-acokb-ground;
>   
>   		interrupt-parent = <&gpx0>;
> -		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
> +		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
>   		pinctrl-names = "default";
>   		pinctrl-0 = <&s2mps11_irq>;
>   

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland