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From:   Icenowy Zheng <icenowy@aosc.io>
To:     Rob Herring <robh+dt@kernel.org>,
        Maxime Ripard <mripard@kernel.org>,
        Chen-Yu Tsai <wens@csie.org>,
        Jernej Skrabec <jernej.skrabec@siol.net>
Cc:     devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, Icenowy Zheng <icenowy@aosc.io>
Subject: [RFC PATCH 02/12] dt-bindings: clk: sunxi-ng: add V833 CCU clock/reset indices headers
Date:   Sat, 12 Dec 2020 12:03:08 +0800
Message-Id: <20201212040318.3640236-1-icenowy@aosc.io>
In-Reply-To: <20201212040157.3639864-1-icenowy@aosc.io>
References: <20201212040157.3639864-1-icenowy@aosc.io>
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Precedence: bulk

As the device tree needs the clock/reset indices, add them to DT binding
headers.

The driver itself will be then added.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 include/dt-bindings/clock/sun8i-v833-ccu.h | 89 ++++++++++++++++++++++
 include/dt-bindings/reset/sun8i-v833-ccu.h | 52 +++++++++++++
 2 files changed, 141 insertions(+)
 create mode 100644 include/dt-bindings/clock/sun8i-v833-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-v833-ccu.h

diff --git a/include/dt-bindings/clock/sun8i-v833-ccu.h b/include/dt-bindings/clock/sun8i-v833-ccu.h
new file mode 100644
index 000000000000..885f3462eab6
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-v833-ccu.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2020 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_V833_H_
+#define _DT_BINDINGS_CLK_SUN8I_V833_H_
+
+#define CLK_CPUX		14
+
+#define CLK_APB1		19
+
+#define CLK_DE			21
+#define CLK_BUS_DE		22
+#define CLK_G2D			23
+#define CLK_BUS_G2D		24
+#define CLK_CE			25
+#define CLK_BUS_CE		26
+#define CLK_VE			27
+#define CLK_BUS_VE		28
+#define CLK_EISE		29
+#define CLK_BUS_EISE		30
+#define CLK_NPU			31
+#define CLK_BUS_NPU		32
+#define CLK_BUS_DMA		33
+#define CLK_BUS_HSTIMER		34
+#define CLK_AVS			35
+#define CLK_BUS_DBG		36
+#define CLK_BUS_PSI		37
+#define CLK_BUS_PWM		38
+#define CLK_MBUS_DMA		40
+#define CLK_MBUS_VE		41
+#define CLK_MBUS_CE		42
+#define CLK_MBUS_TS		43
+#define CLK_MBUS_NAND		44
+#define CLK_MBUS_G2D		45
+#define CLK_MBUS_EISE		46
+#define CLK_MBUS_VDPO		47
+#define CLK_MMC0		49
+#define CLK_MMC1		50
+#define CLK_MMC2		51
+#define CLK_BUS_MMC0		52
+#define CLK_BUS_MMC1		53
+#define CLK_BUS_MMC2		54
+#define CLK_BUS_UART0		55
+#define CLK_BUS_UART1		56
+#define CLK_BUS_UART2		57
+#define CLK_BUS_UART3		58
+#define CLK_BUS_I2C0		59
+#define CLK_BUS_I2C1		60
+#define CLK_BUS_I2C2		61
+#define CLK_BUS_I2C3		62
+#define CLK_SPI0		63
+#define CLK_SPI1		64
+#define CLK_SPI2		65
+#define CLK_BUS_SPI0		66
+#define CLK_BUS_SPI1		67
+#define CLK_BUS_SPI2		68
+#define CLK_EMAC_25M		69
+#define CLK_BUS_EMAC0		70
+#define CLK_BUS_GPADC		71
+#define CLK_BUS_THS		72
+#define CLK_I2S0		73
+#define CLK_I2S1		74
+#define CLK_BUS_I2S0		75
+#define CLK_BUS_I2S1		76
+#define CLK_AUDIO_CODEC_1X	77
+#define CLK_AUDIO_CODEC_4X	78
+#define CLK_BUS_AUDIO_CODEC	79
+#define CLK_USB_OHCI0		80
+#define CLK_USB_PHY0		81
+#define CLK_BUS_OHCI0		82
+#define CLK_BUS_EHCI0		83
+#define CLK_BUS_OTG		84
+#define CLK_MIPI_DSI_DPHY0_HS	85
+#define CLK_MIPI_DSI_HOST0	86
+#define CLK_BUS_MIPI_DSI	87
+#define CLK_BUS_TCON_TOP	88
+#define CLK_TCON_LCD0		89
+#define CLK_BUS_TCON_LCD0	90
+#define CLK_CSI_TOP		91
+#define CLK_CSI_MCLK0		92
+#define CLK_CSI_MCLK1		93
+#define CLK_ISP			94
+#define CLK_BUS_CSI		95
+#define CLK_DSPO		96
+#define CLK_BUS_DSPO		97
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_V833_H_ */
diff --git a/include/dt-bindings/reset/sun8i-v833-ccu.h b/include/dt-bindings/reset/sun8i-v833-ccu.h
new file mode 100644
index 000000000000..fb2b0e3b287f
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-v833-ccu.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN8I_V833_H_
+#define _DT_BINDINGS_RESET_SUN8I_V833_H_
+
+#define RST_MBUS		0
+#define RST_BUS_DE		1
+#define RST_BUS_G2D		2
+#define RST_BUS_CE		3
+#define RST_BUS_VE		4
+#define RST_BUS_EISE		5
+#define RST_BUS_NPU		6
+#define RST_BUS_DMA		7
+#define RST_BUS_HSTIMER		8
+#define RST_BUS_DBG		9
+#define RST_BUS_PSI		10
+#define RST_BUS_PWM		11
+#define RST_BUS_DRAM		12
+#define RST_BUS_MMC0		13
+#define RST_BUS_MMC1		14
+#define RST_BUS_MMC2		15
+#define RST_BUS_UART0		16
+#define RST_BUS_UART1		17
+#define RST_BUS_UART2		18
+#define RST_BUS_UART3		19
+#define RST_BUS_I2C0		20
+#define RST_BUS_I2C1		21
+#define RST_BUS_I2C2		22
+#define RST_BUS_I2C3		23
+#define RST_BUS_SPI0		24
+#define RST_BUS_SPI1		25
+#define RST_BUS_SPI2		26
+#define RST_BUS_EMAC0		27
+#define RST_BUS_GPADC		28
+#define RST_BUS_THS		29
+#define RST_BUS_I2S0		30
+#define RST_BUS_I2S1		31
+#define RST_BUS_AUDIO_CODEC	32
+#define RST_USB_PHY0		33
+#define RST_BUS_OHCI0		34
+#define RST_BUS_EHCI0		35
+#define RST_BUS_OTG		36
+#define RST_BUS_MIPI_DSI	37
+#define RST_BUS_TCON_TOP	38
+#define RST_BUS_TCON_LCD0	39
+#define RST_BUS_CSI		40
+#define RST_BUS_DSPO		41
+
+#endif /* _DT_BINDINGS_RESET_SUN8I_V833_H_ */
-- 
2.28.0