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From:   Qing Zhang <zhangqing@loongson.cn>
To:     Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc:     linux-spi@vger.kernel.org, Huacai Chen <chenhc@lemote.com>,
        Jiaxun Yang <jiaxun.yang@flygoat.com>,
        devicetree@vger.kernel.org, linux-mips@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: [PATCH v3 2/4] spi: ls7a: Add YAML schemas
Date:   Mon, 14 Dec 2020 13:58:52 +0800
Message-Id: <1607925534-8312-2-git-send-email-zhangqing@loongson.cn>
In-Reply-To: <1607925534-8312-1-git-send-email-zhangqing@loongson.cn>
References: <1607925534-8312-1-git-send-email-zhangqing@loongson.cn>
Precedence: bulk

Switch the DT binding to a YAML schema to enable the DT validation.

Signed-off-by: Qing Zhang <zhangqing@loongson.cn>
---
 .../devicetree/bindings/spi/loongson,spi-ls7a.yaml | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/loongson,spi-ls7a.yaml

diff --git a/Documentation/devicetree/bindings/spi/loongson,spi-ls7a.yaml b/Documentation/devicetree/bindings/spi/loongson,spi-ls7a.yaml
new file mode 100644
index 0000000..41691c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/loongson,spi-ls7a.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/spi-ls7a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson LS7A PCH SPI Controller
+
+all0f:
+   - $ref: "spi-controller.yaml#"
+
+maintainers:
+  - Qing Zhang <zhangqing@loongson.cn>
+
+description: |
+  This controller can be found in Loongson-3 systems with LS7A PCH.
+
+properties:
+  "#address-cells": true
+  "#size-cells": true
+
+  compatible:
+    const: loongson,ls7a-spi
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - num-chipselects
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    spi@16,0 {
+        compatible = "pci0014,7a0b.0",
+                        "pci0014,7a0b",
+                        "pciclass088000",
+                        "pciclass0800";
+
+        reg = <0xb000 0x0 0x0 0x0 0x0>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        num-chipselects = <0>;
+    };
+
+...
-- 
2.1.0