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[209.85.167.46]) by smtp.gmail.com with ESMTPSA id f2sm2249967ljc.118.2020.12.14.01.26.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Dec 2020 01:26:42 -0800 (PST) Received: by mail-lf1-f46.google.com with SMTP id x20so8852902lfe.12; Mon, 14 Dec 2020 01:26:42 -0800 (PST) X-Received: by 2002:a2e:6e06:: with SMTP id j6mr9929044ljc.282.1607938002616; Mon, 14 Dec 2020 01:26:42 -0800 (PST) MIME-Version: 1.0 References: <20201202135409.13683-1-andre.przywara@arm.com> <20201202135409.13683-3-andre.przywara@arm.com> <70df5b048c81485053df91a3e53dc840487677e3.camel@aosc.io> In-Reply-To: <70df5b048c81485053df91a3e53dc840487677e3.camel@aosc.io> From: Chen-Yu Tsai Date: Mon, 14 Dec 2020 17:26:31 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/8] pinctrl: sunxi: Add support for the Allwinner H616 pin controller To: Icenowy Zheng Cc: Andre Przywara , Maxime Ripard , Jernej Skrabec , Icenowy Zheng , linux-arm-kernel , linux-sunxi , Linus Walleij , Rob Herring , Yangtao Li , linux-kernel , "open list:GPIO SUBSYSTEM" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Dec 14, 2020 at 12:28 AM Icenowy Zheng wrote: > > 在 2020-12-02星期三的 13:54 +0000,Andre Przywara写道: > > Port A is used for an internal connection to some analogue circuitry > > which looks like an AC200 IP (as in the H6), though this is not > > mentioned in the manual. > > When developing for V831, I found that PIO controller in H616 (and > V831) has the functionality of selecting IO voltage of PF bank (needed > to handle UHS-I). > > How should we model this in PIO driver? I suppose we could expose it as a regulator for the mmc node to consume as its vqmmc-supply? ChenYu