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From:   "Sia, Jee Heng" <jee.heng.sia@intel.com>
To:     Rob Herring <robh@kernel.org>
CC:     "vkoul@kernel.org" <vkoul@kernel.org>,
        "Eugeniy.Paltsev@synopsys.com" <Eugeniy.Paltsev@synopsys.com>,
        "andriy.shevchenko@linux.intel.com" 
        <andriy.shevchenko@linux.intel.com>,
        "dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: RE: [PATCH v6 01/16] dt-bindings: dma: Add YAML schemas for
 dw-axi-dmac
Thread-Topic: [PATCH v6 01/16] dt-bindings: dma: Add YAML schemas for
 dw-axi-dmac
Thread-Index: AQHW0mvNhKu2snl0SUeg5ahzlza7gan3yMHw
Date:   Tue, 15 Dec 2020 08:08:55 +0000
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References: <20201211004642.25393-1-jee.heng.sia@intel.com>
 <20201211004642.25393-2-jee.heng.sia@intel.com>
 <20201214225211.GA2525287@robh.at.kernel.org>
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> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 15 December 2020 6:52 AM
> To: Sia, Jee Heng <jee.heng.sia@intel.com>
> Cc: vkoul@kernel.org; Eugeniy.Paltsev@synopsys.com;
> andriy.shevchenko@linux.intel.com; dmaengine@vger.kernel.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v6 01/16] dt-bindings: dma: Add YAML schemas
> for dw-axi-dmac
>=20
> On Fri, Dec 11, 2020 at 08:46:27AM +0800, Sia Jee Heng wrote:
> > YAML schemas Device Tree (DT) binding is the new format for DT to
> > replace the old format. Introduce YAML schemas DT binding for
> > dw-axi-dmac and remove the old version.
> >
> > Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
> > ---
> >  .../bindings/dma/snps,dw-axi-dmac.txt         |  39 ------
> >  .../bindings/dma/snps,dw-axi-dmac.yaml        | 125
> ++++++++++++++++++
> >  2 files changed, 125 insertions(+), 39 deletions(-)  delete mode
> > 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-
> dmac.txt
> >  create mode 100644
> > Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>=20
>=20
> > diff --git
> > a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> > b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> > new file mode 100644
> > index 000000000000..61ad37a3f559
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-
> dmac.yaml
> > @@ -0,0 +1,125 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> 1.2
> > +---
> > +$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Synopsys DesignWare AXI DMA Controller
> > +
> > +maintainers:
> > +  - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> > +
> > +description:
> > +  Synopsys DesignWare AXI DMA Controller DT Binding
>=20
> allOf:
>   - $ref: dma-controller.yaml#
[>>] Thanks. Will include it in next version.
>=20
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - snps,axi-dma-1.01a
> > +
> > +  reg:
> > +    items:
> > +      - description: Address range of the DMAC registers
> > +
> > +  reg-names:
> > +    items:
> > +      - const: axidma_ctrl_regs
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: Bus Clock
> > +      - description: Module Clock
> > +
> > +  clock-names:
> > +    items:
> > +      - const: core-clk
> > +      - const: cfgr-clk
> > +
> > +  '#dma-cells':
> > +    const: 1
> > +
> > +  dma-channels:
> > +    description: |
> > +      Number of channels supported by hardware.
>=20
> Already described in dma-controller.yaml
[>>] Thanks. Will remove the description in next version but keep the const=
raint.
>=20
> > +    minimum: 1
> > +    maximum: 8
> > +
> > +  snps,dma-masters:
> > +    description: |
> > +      Number of AXI masters supported by the hardware.
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [1, 2]
> > +    default: 2
> > +
> > +  snps,data-width:
> > +    description: |
> > +      AXI data width supported by hardware.
> > +      (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [0, 1, 2, 3, 4, 5, 6]
> > +    default: 4
> > +
> > +  snps,priority:
> > +    description: |
> > +      Channel priority specifier associated with the DMA channels.
> > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > +    minItems: 1
> > +    maxItems: 8
> > +    default: [0, 1, 2, 3]
> > +
> > +  snps,block-size:
> > +    description: |
> > +      Channel block size specifier associated with the DMA channels.
> > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > +    minItems: 1
> > +    maxItems: 8
> > +    default: [4096, 4096, 4096, 4096]
> > +
> > +  snps,axi-max-burst-len:
> > +    description: |
> > +      Restrict master AXI burst length by value specified in this
> property.
> > +      If this property is missing the maximum AXI burst length
> supported by
> > +      DMAC is used.
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    minimum: 1
> > +    maximum: 256
> > +    default: 16
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - interrupts
> > +  - '#dma-cells'
>=20
> Already required.
[>>] Hope the comment "already required" is for the below properties.=20
>=20
> > +  - dma-channels
> > +  - snps,dma-masters
> > +  - snps,data-width
> > +  - snps,priority
> > +  - snps,block-size
>=20
> How can these be both required and have a default?
[>>] Thanks. Those are required properties, perhaps I should remove the def=
ault field to avoid misunderstanding.=20
>=20
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +     #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +     #include <dt-bindings/interrupt-controller/irq.h>
> > +     /* example with snps,dw-axi-dmac */
> > +     dmac: dma-controller@80000 {
> > +         compatible =3D "snps,axi-dma-1.01a";
> > +         reg =3D <0x80000 0x400>;
> > +         clocks =3D <&core_clk>, <&cfgr_clk>;
> > +         clock-names =3D "core-clk", "cfgr-clk";
> > +         interrupt-parent =3D <&intc>;
> > +         interrupts =3D <27>;
> > +         #dma-cells =3D <1>;
> > +         dma-channels =3D <4>;
> > +         snps,dma-masters =3D <2>;
> > +         snps,data-width =3D <3>;
> > +         snps,block-size =3D <4096 4096 4096 4096>;
> > +         snps,priority =3D <0 1 2 3>;
> > +         snps,axi-max-burst-len =3D <16>;
> > +     };
> > --
> > 2.18.0
> >