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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id o6sm4767421oon.7.2020.12.15.08.03.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 08:03:44 -0800 (PST) Received: (nullmailer pid 3935079 invoked by uid 1000); Tue, 15 Dec 2020 16:03:43 -0000 Date: Tue, 15 Dec 2020 10:03:43 -0600 From: Rob Herring To: Sowjanya Komatineni Cc: tudor.ambarus@microchip.com, p.yadav@ti.com, robh+dt@kernel.org, bbrezillon@kernel.org, linux-spi@vger.kernel.org, lukas@wunner.de, broonie@kernel.org, linux-tegra@vger.kernel.org, jonathanh@nvidia.com, thierry.reding@gmail.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 1/9] dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM Message-ID: <20201215160343.GA3935026@robh.at.kernel.org> References: <1607721363-8879-1-git-send-email-skomatineni@nvidia.com> <1607721363-8879-2-git-send-email-skomatineni@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1607721363-8879-2-git-send-email-skomatineni@nvidia.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 11 Dec 2020 13:15:55 -0800, Sowjanya Komatineni wrote: > Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled > when using DDR interface mode. > > This patch adds clock ID for this to dt-binding. > > Signed-off-by: Sowjanya Komatineni > --- > include/dt-bindings/clock/tegra210-car.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Rob Herring