Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750747AbWIDKyn (ORCPT ); Mon, 4 Sep 2006 06:54:43 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751312AbWIDKyn (ORCPT ); Mon, 4 Sep 2006 06:54:43 -0400 Received: from outpipe-village-512-1.bc.nu ([81.2.110.250]:14806 "EHLO lxorguk.ukuu.org.uk") by vger.kernel.org with ESMTP id S1750747AbWIDKym (ORCPT ); Mon, 4 Sep 2006 06:54:42 -0400 Subject: Re: 2.6.18-rc5 + pata-drivers on MSI K9N Ultra report, AMD64 From: Alan Cox To: Krzysztof Halasa Cc: linux-kernel@vger.kernel.org, Jeff Garzik In-Reply-To: References: <1157234944.6271.400.camel@localhost.localdomain> Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Mon, 04 Sep 2006 12:16:35 +0100 Message-Id: <1157368595.30801.23.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.6.2 (2.6.2-1.fc5.5) Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 716 Lines: 22 Ar Sul, 2006-09-03 am 00:45 +0200, ysgrifennodd Krzysztof Halasa: > Hmmm... is it that 0x62, isn't it? > > static struct pci_bits amd_enable_bits[] = { > { 0x40, 1, 0x02, 0x02 }, > { 0x40, 1, 0x01, 0x01 } > }; The Nvidia ones have the register base at 0x50. Looking at the code I think its just a case of adding an 0x50 based enable_bits test to nv_pre_reset, and I'll fold that in now. -- VGER BF report: U 0.474419 - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/