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From:   Dmitry Osipenko <digetx@gmail.com>
To:     Thierry Reding <thierry.reding@gmail.com>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        Mark Brown <broonie@kernel.org>,
        Liam Girdwood <lgirdwood@gmail.com>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        Mauro Carvalho Chehab <mchehab@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Peter Geis <pgwipeout@gmail.com>,
        Nicolas Chauvet <kwizart@gmail.com>,
        Krzysztof Kozlowski <krzk@kernel.org>,
        "Rafael J. Wysocki" <rjw@rjwysocki.net>,
        Kevin Hilman <khilman@kernel.org>,
        Peter De Schrijver <pdeschrijver@nvidia.com>,
        Viresh Kumar <vireshk@kernel.org>,
        Stephen Boyd <sboyd@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>
Cc:     devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org,
        linux-media@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-clk@vger.kernel.org
Subject: [PATCH v2 23/48] soc/tegra: pmc: Pulse resets after removing power clamp
Date:   Thu, 17 Dec 2020 21:06:13 +0300
Message-Id: <20201217180638.22748-24-digetx@gmail.com>
In-Reply-To: <20201217180638.22748-1-digetx@gmail.com>
References: <20201217180638.22748-1-digetx@gmail.com>
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The GR3D1 hardware unit needs to pulse hardware reset after removing power
clamp, otherwise reset won't be deasserted. Hence give reset a pulse after
removing the clamp. This stayed unnoticed previously because power
management wasn't supported by the 3D driver until recently and all power
gates are usually ungated after bootloader by default.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/soc/tegra/pmc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index fd2ba3c59178..985373ce52b1 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -654,6 +654,14 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,
 
 	usleep_range(10, 20);
 
+	/*
+	 * Some hardware blocks may need a 0->1->0 reset pulse in order
+	 * to propagate the reset, Tegra30 3D1 is one example.
+	 */
+	err = reset_control_reset(pg->reset);
+	if (err)
+		goto powergate_off;
+
 	if (pg->pmc->soc->needs_mbist_war)
 		err = tegra210_clk_handle_mbist_war(pg->id);
 	if (err)
-- 
2.29.2