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Subject: Re: [PATCH 2/6] dt-bindings: clk: mstar msc313 mpll binding description
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        w@1wt.eu, Daniel Palmer <daniel@0x0f.com>
To:     Daniel Palmer <daniel@0x0f.com>, devicetree@vger.kernel.org,
        linux-clk@vger.kernel.org
Date:   Sat, 19 Dec 2020 19:39:20 -0800
Message-ID: <160843556037.1580929.13575770228476494246@swboyd.mtv.corp.google.com>
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Quoting Daniel Palmer (2020-11-14 05:50:40)
> Add a binding description for the MStar/SigmaStar MPLL clock block.
>=20
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
> ---
>  .../bindings/clock/mstar,msc313-mpll.yaml     | 58 +++++++++++++++++++
>  MAINTAINERS                                   |  1 +
>  2 files changed, 59 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/mstar,msc313-=
mpll.yaml
>=20
> diff --git a/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.ya=
ml b/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml
> new file mode 100644
> index 000000000000..9ddc1163b31b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MStar/Sigmastar MSC313 MPLL
> +
> +maintainers:
> +  - Daniel Palmer <daniel@thingy.jp>
> +
> +description: |
> +  The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block th=
at
> +  takes the external xtal input and multiplies it to create a high
> +  frequency clock and divides that down into a number of clocks that
> +  peripherals use.
> +
> +properties:
> +  compatible:
> +    const: mstar,msc313-mpll
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-output-names:
> +    minItems: 8
> +    maxItems: 8
> +    description: |
> +      This should provide a name for the internal PLL clock and then
> +      a name for each of the divided outputs.

Is this necessary?

> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - "#clock-cells"
> +  - clocks
> +  - clock-output-names
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    mpll@206000 {
> +        compatible =3D "mstar,msc313-mpll";
> +        reg =3D <0x206000 0x200>;
> +        #clock-cells =3D <1>;
> +        clocks =3D <&xtal>;
> +        clock-output-names =3D "mpll", "mpll_div_2",
> +                             "mpll_div_3", "mpll_div_4",
> +                             "mpll_div_5", "mpll_div_6",
> +                             "mpll_div_7", "mpll_div_10";

It looks like it can be derived in the driver.