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From:   Rob Herring <robh@kernel.org>
Date:   Mon, 21 Dec 2020 09:06:33 -0700
Message-ID: <CAL_JsqKdzu8EgY-pqxH+ZyDh3ALJGccqgPuj=cc==SGbMvYZJw@mail.gmail.com>
Subject: Re: [PATCH] PCI: dwc: Add upper limit address for outbound iATU
To:     Shradha Todi <shradha.t@samsung.com>
Cc:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        PCI <linux-pci@vger.kernel.org>,
        Jingoo Han <jingoohan1@gmail.com>,
        Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Pankaj Dubey <pankaj.dubey@samsung.com>
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On Sun, Dec 20, 2020 at 6:56 PM Shradha Todi <shradha.t@samsung.com> wrote:
>
> The size parameter is unsigned long type which can accept
> size > 4GB. In that case, the upper limit address must be
> programmed. Add support to program the upper limit
> address and set INCREASE_REGION_SIZE in case size > 4GB.

Not all DWC h/w versions have the upper register and bit. Is it safe
to write to the non-existent register?

>
> Signed-off-by: Shradha Todi <shradha.t@samsung.com>
> ---
>  drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++--
>  drivers/pci/controller/dwc/pcie-designware.h | 1 +
>  2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 28c56a1..7eba3b2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -290,12 +290,16 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
>                            upper_32_bits(cpu_addr));
>         dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
>                            lower_32_bits(cpu_addr + size - 1));
> +       dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT,
> +                          upper_32_bits(cpu_addr + size - 1));

If not safe, perhaps only write if non-zero.

>         dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
>                            lower_32_bits(pci_addr));
>         dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
>                            upper_32_bits(pci_addr));
> -       dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
> -                          PCIE_ATU_FUNC_NUM(func_no));
> +       val = type | PCIE_ATU_FUNC_NUM(func_no);
> +       val = upper_32_bits(size - 1) ?
> +               val | PCIE_ATU_INCREASE_REGION_SIZE : val;
> +       dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
>         dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
>
>         /*
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index b09329b..28b72fb 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -106,6 +106,7 @@
>  #define PCIE_ATU_DEV(x)                        FIELD_PREP(GENMASK(23, 19), x)
>  #define PCIE_ATU_FUNC(x)               FIELD_PREP(GENMASK(18, 16), x)
>  #define PCIE_ATU_UPPER_TARGET          0x91C
> +#define PCIE_ATU_UPPER_LIMIT           0x924
>
>  #define PCIE_MISC_CONTROL_1_OFF                0x8BC
>  #define PCIE_DBI_RO_WR_EN              BIT(0)
> --
> 2.7.4
>