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X-MS-Exchange-AntiSpam-MessageData: =?utf-8?B?TG4vQ0hVc1hlaGtGWU1OMUJIdWh1QmprZCs5YnduTmpUTVdLZ3g2TlZla0w0?= =?utf-8?B?K3BMaGp0aWxmb2xEanRhdXFmZGpmcHd6K09BSmpvNlFpbUd1VkJuVnBjbjRP?= =?utf-8?B?bVBNNGQ2RDNOWSt1ZzNHUVc2VTRIK2ZBWWY4cnBPa1B3RU0xVHcvdS9jR1dL?= =?utf-8?B?L0Q0WmdYYVZueVJmUklGa0QzS0dTaTkwOG1EZy8yTkh4K0doa3BBWk54L3Nr?= =?utf-8?B?THdzZDMzdDJ5TlhYV3FhY3hxMDdjczYxOTVXWkR5UHF3K3R5UVhvQUg3RE8y?= =?utf-8?B?Y1o1aUlmUHp3OWRFamRzU3YzRCtrTkVLYk1ScitvTXorNmhoM2VudXBWQTZt?= =?utf-8?B?c2lEMU1COVV3czBqMXJycVFiZEdCNHRTaHJxMWF1cnRkL1VNWHc1bElvTE1l?= =?utf-8?B?Y2Z4TlRjS2FkOE9TRGp3aDlLVkxxWFBYU1NLOFk4TEtCVTdaRzhOblpKQjE2?= =?utf-8?B?aE0yTXgyT3JJNHM5N29pMjI3OXBpWnN1SjIzV3AzQlNiQjhVZkwxMVh4cDFO?= =?utf-8?B?dlRKL01hNXU0WmpWZWliNTB6SWJjQUx0Z016RncrZmR5WEhESVpWRmJjcUJN?= =?utf-8?B?UkpYQlRXeVdmd2xJaUQ3RkhLREFQc3lyTm9OeEZ1Y2xXQWxrUmxuVlc0WGpo?= =?utf-8?B?MWoxRTNWUFRMalVKQVNVaFo2R3pMMHJaa2p5OFBCeUo0VW9PMTdoWk43V011?= =?utf-8?B?RktEZ0hSdXRYK1JDcFhrK1hzVC9CWThyNlBFUlh5SHdpc3dnbGVpdjhZQkZK?= =?utf-8?B?UHY2S1FseTlzd0Y3NEJSUGpEL0orbEd5dVBBR3E0UW5EMGUwSUNPaS9YZE9p?= =?utf-8?B?T0RNaW5UaGQ3UEZSeS93bmJ1clV2b0duaEVFR200bkRQOFpyZW53WThDbXV3?= =?utf-8?B?ZzBoa2cxTWtFQUJOZVowZGlneHRZc0FMSjVka1lodHFkTnMwamFjZktHZS9G?= =?utf-8?B?aFYwVXE2bGE3UE5XMXJ3akVEOUVZVkhmNWsrbDBPaHhJVGVtNWtOTGdIbVdE?= =?utf-8?B?YTV3NHFIbm15UEtIS29Jay8vcGFjdzArSFlNM3dMNVVvMCt4cmRvc1piMkFj?= =?utf-8?B?SXl0Y0N2Um5Qb20rNDRjT3dyc0VVMUN0dHFZeW95Szl1MmUrTzlSZDRsU0V0?= =?utf-8?B?S0gzei83elhmbnVzejQvS0Rxcm4vQ1JmbDMrYlB6eW1HRmc4TWVzQUtLWXpp?= =?utf-8?B?STVibXJHZDBzanF2Q242MVd5ZEpVaUQ1ZUorM3ZpUml1WDFvdzBpQjloWU96?= =?utf-8?B?eHUzdXBYWU96bnRxcjZNZG5JSTNTOWthNmVOUzBpa2d0VWsyV2p1bUdJSkh3?= =?utf-8?Q?qCOluWEsHZ6EU=3D?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthSource: SN1PR12MB2560.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Dec 2020 16:14:44.5957 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-Network-Message-Id: 96a1fd05-6071-477d-42d0-08d8a694b22d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nKz8N6FruDGKnW0WAN08Di9LnMhGy9uPJZWdWJt2SdoUOu4g45lVROfVVfbbJwFk X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR12MB2383 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/9/20 5:11 PM, Jim Mattson wrote: > On Wed, Dec 9, 2020 at 2:39 PM Babu Moger wrote: >> >> >> >> On 12/7/20 5:22 PM, Jim Mattson wrote: >>> On Mon, Dec 7, 2020 at 2:38 PM Babu Moger wrote: >>>> >>>> Newer AMD processors have a feature to virtualize the use of the SPEC_CTRL >>>> MSR. This feature is identified via CPUID 0x8000000A_EDX[20]. When present, >>>> the SPEC_CTRL MSR is automatically virtualized and no longer requires >>>> hypervisor intervention. >>>> >>>> Signed-off-by: Babu Moger >>>> --- >>>> arch/x86/include/asm/cpufeatures.h | 1 + >>>> 1 file changed, 1 insertion(+) >>>> >>>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h >>>> index dad350d42ecf..d649ac5ed7c7 100644 >>>> --- a/arch/x86/include/asm/cpufeatures.h >>>> +++ b/arch/x86/include/asm/cpufeatures.h >>>> @@ -335,6 +335,7 @@ >>>> #define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ >>>> #define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ >>>> #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ >>>> +#define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */ >>> >>> Shouldn't this bit be reported by KVM_GET_SUPPORTED_CPUID when it's >>> enumerated on the host? >> >> Jim, I am not sure if this needs to be reported by >> KVM_GET_SUPPORTED_CPUID. I dont see V_VMSAVE_VMLOAD or VGIF being reported >> via KVM_GET_SUPPORTED_CPUID. Do you see the need for that? > > Every little bit helps. No, it isn't *needed*. But then again, this > entire patchset isn't *needed*, is it? > Working on v2 of these patches. Saw this code comment(in arch/x86/kvm/cpuid.c) on about exposing SVM features to the guest. /* * Hide all SVM features by default, SVM will set the cap bits for * features it emulates and/or exposes for L1. */ kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); Should we go ahead with the changes here? Thanks Babu