Received: by 2002:a05:6a10:f347:0:0:0:0 with SMTP id d7csp6510521pxu; Thu, 24 Dec 2020 04:28:49 -0800 (PST) X-Google-Smtp-Source: ABdhPJyc3fY7NJbLdsfKBtjSI1vSBGs5ZivX6mGl2hWcKJOLqVn+8YFbBLa22f2+++YxiOhchTtB X-Received: by 2002:aa7:c253:: with SMTP id y19mr28047564edo.179.1608812929622; Thu, 24 Dec 2020 04:28:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608812929; cv=none; d=google.com; s=arc-20160816; b=rXUm1BFEmvstcVGFB5BiEjDQ7NSmvuf9ewLmbJWPbpJ0UMf2PGuexvdAFKY4+/mE7M 7P/cGiVoxnYV+Le8D1azLCn8R/KQCYDfYaI7TvtJGrnlMmJ/0E1f8W4TDSxImqdyTU49 7VSQM25YxG5O41B2AXilhyXSs8LysI7r0W+DM0mUh2RxoyWilB1cw7Fil1c4AimoIunc 6im5Iwv8QqesxMEHO1MNK7/k16tXvtm130FAD8FH6eI5NKyGtzIBpCko8jBaA3FWkEKU fk2kjUK3ok/iSz0FkzhEmIUNxu3t+ibfxWV5tJovKBjz1X8MGrHYJlcqsnzCmx+Mold1 48Bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=oZ6uRQ/x1yVz5fy9ffQeAQw72YVA+uxTMjOkxV7Sd/s=; b=vUz55AWOImkLRIqylM/f+OVyosrT8903/xqGYpBqyT+DhqOmZ0AyMFXmZ/W5ipvdmD g49bCLTU1cv/j//2Z1NmmuFIpgMWbKE6DPCCRIrTHoSp/XEVEkUptkTiquB7CeGa9h98 ZOpdCnnLwz3u7bs9u2kSIl6kmS6988D4ySe0hLRn0WayVA6zAY0JrDKGmu+VLpeh3ZZy vUtrP0BnsZlpIMjdqHzGsAAJrLD0CVnjtwXZPaXSeuVfMFlTOU4BYde+U68RW9gV3S/B Lx63d9bx56xA4heefmTH+q+tGegOJNurWxP8DOyCwAul19TrxZ27pnqO4wQ+AiO1pedM YOHg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k17si13742181ejq.626.2020.12.24.04.28.27; Thu, 24 Dec 2020 04:28:49 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728316AbgLXM1E (ORCPT + 99 others); Thu, 24 Dec 2020 07:27:04 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:60167 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726746AbgLXM1E (ORCPT ); Thu, 24 Dec 2020 07:27:04 -0500 X-UUID: cd4c9f1888c4451b88cd7fff41c16f91-20201224 X-UUID: cd4c9f1888c4451b88cd7fff41c16f91-20201224 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1540264706; Thu, 24 Dec 2020 20:26:16 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 24 Dec 2020 20:26:13 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 24 Dec 2020 20:26:13 +0800 From: To: CC: , , , , , , , Subject: i2c: mediatek: Fix apdma and i2c hand-shake timeout Date: Thu, 24 Dec 2020 20:26:07 +0800 Message-ID: <1608812767-3254-1-git-send-email-qii.wang@mediatek.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Qii Wang With the apdma remove hand-shake signal, it requirs special operation timing to reset i2c manually, otherwise the interrupt will not be triggered, i2c transmission will be timeout. Signed-off-by: Qii Wang --- drivers/i2c/busses/i2c-mt65xx.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) base Message ID: 1605701861-30800-1-git-send-email-qii.wang@mediatek.com diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index 6f61595..2ffd2f3 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -38,6 +38,7 @@ #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 #define I2C_IO_CONFIG_PUSH_PULL 0x0000 #define I2C_SOFT_RST 0x0001 +#define I2C_HANDSHAKE_RST 0x0020 #define I2C_FIFO_ADDR_CLR 0x0001 #define I2C_DELAY_LEN 0x0002 #define I2C_TIME_CLR_VALUE 0x0000 @@ -45,6 +46,7 @@ #define I2C_WRRD_TRANAC_VALUE 0x0002 #define I2C_RD_TRANAC_VALUE 0x0001 #define I2C_SCL_MIS_COMP_VALUE 0x0000 +#define I2C_CHN_CLR_FLAG 0x0000 #define I2C_DMA_CON_TX 0x0000 #define I2C_DMA_CON_RX 0x0001 @@ -54,7 +56,9 @@ #define I2C_DMA_START_EN 0x0001 #define I2C_DMA_INT_FLAG_NONE 0x0000 #define I2C_DMA_CLR_FLAG 0x0000 +#define I2C_DMA_WARM_RST 0x0001 #define I2C_DMA_HARD_RST 0x0002 +#define I2C_DMA_HANDSHAKE_RST 0x0004 #define MAX_SAMPLE_CNT_DIV 8 #define MAX_STEP_CNT_DIV 64 @@ -475,11 +479,24 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c) { u16 control_reg; - writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); - udelay(50); - writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); - - mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); + if (i2c->dev_comp->dma_sync) { + writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST); + udelay(10); + writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); + udelay(10); + writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST, + i2c->pdmabase + OFFSET_RST); + mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST, + OFFSET_SOFTRESET); + udelay(10); + writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); + mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); + } else { + writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); + udelay(50); + writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); + mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); + } /* Set ioconfig */ if (i2c->use_push_pull) -- 1.9.1