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From:   Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To:     linux-amlogic@lists.infradead.org, jbrunet@baylibre.com
Cc:     mturquette@baylibre.com, sboyd@kernel.org,
        linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org,
        Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH 0/3] clk: meson: three small clk-pll fixes
Date:   Sat, 26 Dec 2020 13:15:53 +0100
Message-Id: <20201226121556.975418-1-martin.blumenstingl@googlemail.com>
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Hi Jerome,

while working on some changes for the 32-bit SoCs I hit a corner-case
in the HDMI PLL: there's some rate doubling going. The PLL only locks
in a specific rate range but the M/N table is not aware of that. This
means for now (I am planning to fix that) that we can end up in a 
ituation where the PLL doesn't lock and meson_clk_pll_set_rate() is
supposed to still behave in this case. So here's three small patches
for that.

For me it's fine to queue these patches for -next. I am not aware of
any breakage upstream, only some of my pending patches prefer to have
these fixes.

Slightly unrelated: if you know anything about that clock doubling then
please let me know!


Best regards,
Martin


Martin Blumenstingl (3):
  clk: meson: clk-pll: fix initializing the old rate (fallback) for a
    PLL
  clk: meson: clk-pll: make "ret" a signed integer
  clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()

 drivers/clk/meson/clk-pll.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

-- 
2.29.2