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[23.128.96.18]) by mx.google.com with ESMTP id v5si24192617eda.107.2020.12.29.11.44.53; Tue, 29 Dec 2020 11:45:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@basnieuwenhuizen.nl header.s=google header.b=CA5qAg67; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726277AbgL2TnY (ORCPT + 99 others); Tue, 29 Dec 2020 14:43:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726178AbgL2TnY (ORCPT ); Tue, 29 Dec 2020 14:43:24 -0500 Received: from mail-il1-x12d.google.com (mail-il1-x12d.google.com [IPv6:2607:f8b0:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B134BC061574 for ; Tue, 29 Dec 2020 11:42:43 -0800 (PST) Received: by mail-il1-x12d.google.com with SMTP id q5so13018725ilc.10 for ; Tue, 29 Dec 2020 11:42:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=basnieuwenhuizen.nl; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Oekv1J5QG7HQ3jpbahBJYVPd5uN5IoF/8wAYXXEPdeY=; b=CA5qAg67Nub4Grsajvru4ROzGio57N4pcnmkQtFTyXsMiUXWKIWxKpPs1d9O3wLv3l WjzzPnSKAMWF1w06/8YA2KfhhgOn1k4gAoZWpa7GIdB/9++2cdXjs7tAeBWySlsX8uYR yNPlKs0f9DGDABxVTPD2t633C7tHnloPNgQoFvUBqty43qLmWHoL45kF8jVSyOTYeiSB VSaJtXwxgoOEf9dJtoP+5szcRjPrM8sEMUH9jpB00mGEGq3XMTAl7odRhTHrq9bLPXny IWJvYFrIC7ni+hNT6TuU3SUHO2MpTZny0vttTvgDrTUOi8r7FxcXUcwDKhjRjXPzHml5 o6pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Oekv1J5QG7HQ3jpbahBJYVPd5uN5IoF/8wAYXXEPdeY=; b=Koo6e9yGrURXuPRNu/fQOIvgW6729wP7w2zwvr4FRfiPlgpbkzXhKEmY/chLVyvJTL rTLrQPLAq920CPBPljbkGEgVGEylQ4EHcBrCzH6eH2Y8WZiUKwy73aEzW3XPGYozAVSA qhC1H8BFrYr44P0WCnfsoyoEXHRqgP7tv1tSAfSFzoM4ZR/oBTsDrGgkiMZMdV01g4wP zqmUr2cUIDGm/TBHsRvbQcI2MYgzUhOSHsq/76zcOODxjPqf60H0QeIvFzRFHb9ysYL1 LjoKtQBI1+2P+G1nqW5/8w/XPSFDdrMypJahQR7a+R5xivkynXTjRLUP7wQ5k+BQbeFP 5F8w== X-Gm-Message-State: AOAM533STs5Rp4QOgV/Pgm19IVTkb3eUT0RMOFMvT/RxiTDwxA0h8qVa TEosSwCOnnngsjZDuPdlaCY3gujowNyDl0lY9WYGl0+4+7oEkw== X-Received: by 2002:a05:6e02:ca5:: with SMTP id 5mr48244379ilg.40.1609270962974; Tue, 29 Dec 2020 11:42:42 -0800 (PST) MIME-Version: 1.0 References: <20201228125020.963311703@linuxfoundation.org> <20201228125051.345050198@linuxfoundation.org> In-Reply-To: <20201228125051.345050198@linuxfoundation.org> From: Bas Nieuwenhuizen Date: Tue, 29 Dec 2020 20:42:50 +0100 Message-ID: Subject: Re: [PATCH 5.10 635/717] drm/amd/display: Honor the offset for plane 0. To: Greg Kroah-Hartman Cc: LKML , stable@vger.kernel.org, Alex Deucher , Nicholas Kazlauskas Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Greg, Someone bisected a non-booting computer with 5.10.4-rc1 to this commit. Would it be possible to back out of backporting this commit (was backported to 5.4 and 5.10)? I suspect we may need 53f4cb8b5580a20d01449a7d8e1cbfdaed9ff6b6 to be picked too to avoid regressing, but I'm not sure about process (e.g. timeline to confirm things) here and a not booting computer is really bad. Thanks, Bas On Mon, Dec 28, 2020 at 3:28 PM Greg Kroah-Hartman wrote: > > From: Bas Nieuwenhuizen > > commit be7b9b327e79cd2db07b659af599867b629b2f66 upstream. > > With modifiers I'd like to support non-dedicated buffers for > images. > > Signed-off-by: Bas Nieuwenhuizen > Reviewed-by: Alex Deucher > Reviewed-by: Nicholas Kazlauskas > Cc: stable@vger.kernel.org # 5.1.0 > Signed-off-by: Alex Deucher > Signed-off-by: Greg Kroah-Hartman > > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -3746,6 +3746,7 @@ fill_plane_dcc_attributes(struct amdgpu_ > struct dc *dc = adev->dm.dc; > struct dc_dcc_surface_param input; > struct dc_surface_dcc_cap output; > + uint64_t plane_address = afb->address + afb->base.offsets[0]; > uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); > uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; > uint64_t dcc_address; > @@ -3789,7 +3790,7 @@ fill_plane_dcc_attributes(struct amdgpu_ > AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1; > dcc->independent_64b_blks = i64b; > > - dcc_address = get_dcc_address(afb->address, info); > + dcc_address = get_dcc_address(plane_address, info); > address->grph.meta_addr.low_part = lower_32_bits(dcc_address); > address->grph.meta_addr.high_part = upper_32_bits(dcc_address); > > @@ -3820,6 +3821,8 @@ fill_plane_buffer_attributes(struct amdg > address->tmz_surface = tmz_surface; > > if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { > + uint64_t addr = afb->address + fb->offsets[0]; > + > plane_size->surface_size.x = 0; > plane_size->surface_size.y = 0; > plane_size->surface_size.width = fb->width; > @@ -3828,9 +3831,10 @@ fill_plane_buffer_attributes(struct amdg > fb->pitches[0] / fb->format->cpp[0]; > > address->type = PLN_ADDR_TYPE_GRAPHICS; > - address->grph.addr.low_part = lower_32_bits(afb->address); > - address->grph.addr.high_part = upper_32_bits(afb->address); > + address->grph.addr.low_part = lower_32_bits(addr); > + address->grph.addr.high_part = upper_32_bits(addr); > } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { > + uint64_t luma_addr = afb->address + fb->offsets[0]; > uint64_t chroma_addr = afb->address + fb->offsets[1]; > > plane_size->surface_size.x = 0; > @@ -3851,9 +3855,9 @@ fill_plane_buffer_attributes(struct amdg > > address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; > address->video_progressive.luma_addr.low_part = > - lower_32_bits(afb->address); > + lower_32_bits(luma_addr); > address->video_progressive.luma_addr.high_part = > - upper_32_bits(afb->address); > + upper_32_bits(luma_addr); > address->video_progressive.chroma_addr.low_part = > lower_32_bits(chroma_addr); > address->video_progressive.chroma_addr.high_part = > >