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(p200300ea8f06550040d3850424f3bef8.dip0.t-ipconnect.de. [2003:ea:8f06:5500:40d3:8504:24f3:bef8]) by smtp.googlemail.com with ESMTPSA id l8sm6550598wmf.35.2020.12.30.01.12.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Dec 2020 01:12:07 -0800 (PST) Subject: Re: Registering IRQ for MT7530 internal PHYs To: DENG Qingfang Cc: "David S. Miller" , Andrew Lunn , Florian Fainelli , Jakub Kicinski , Landen Chao , Marc Zyngier , Matthias Brugger , Philipp Zabel , Russell King , Sean Wang , Thomas Gleixner , Vivien Didelot , Vladimir Oltean , linux-kernel@vger.kernel.org, netdev , Weijie Gao , Chuanhong Guo , Linus Walleij , =?UTF-8?Q?Ren=c3=a9_van_Dorst?= References: <20201230042208.8997-1-dqfext@gmail.com> From: Heiner Kallweit Message-ID: Date: Wed, 30 Dec 2020 10:12:03 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30.12.2020 10:07, DENG Qingfang wrote: > Hi Heiner, > Thanks for your reply. > > On Wed, Dec 30, 2020 at 3:39 PM Heiner Kallweit wrote: >> I don't think that's the best option. > > I'm well aware of that. > >> You may want to add a PHY driver for your chip. Supposedly it >> supports at least PHY suspend/resume. You can use the RTL8366RB >> PHY driver as template. > > There's no MediaTek PHY driver yet. Do we really need a new one just > for the interrupts? > Not only for the interrupts. The genphy driver e.g. doesn't support PHY suspend/resume. And the PHY driver needs basically no code, just set the proper callbacks. >>> + dev_info_ratelimited(priv->dev, "interrupt status: 0x%08x\n", val); >>> + dev_info_ratelimited(priv->dev, "interrupt enable: 0x%08x\n", mt7530_read(priv, MT7530_SYS_INT_EN)); >>> + >> This is debug code to be removed in the final version? > > Yes. > >>> + for (phy = 0; phy < MT7530_NUM_PHYS; phy++) { >>> + if (val & BIT(phy)) { >>> + unsigned int child_irq; >>> + >>> + child_irq = irq_find_mapping(priv->irq_domain, phy); >>> + handle_nested_irq(child_irq); >>> + handled = true; >>> + } >>> + } >>> + >>> + return handled ? IRQ_HANDLED : IRQ_NONE; >> >> IRQ_RETVAL() could be used here. > > Good to know :) > >> >>> +} >>> + >>> +static void mt7530_irq_mask(struct irq_data *d) >>> +{ >>> + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); >>> + >>> + priv->irq_enable &= ~BIT(d->hwirq); >> >> Here you don't actually do something. HW doesn't support masking >> interrupt generation for a port? > > priv->irq_enable will be written to MT7530_SYS_INT_EN in > mt7530_irq_bus_sync_unlock. You can think of it as an inverted mask. >