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Message-ID: <45000076.4070005@gmail.com>
Date: Thu, 07 Sep 2006 13:20:22 +0200
From: Tejun Heo <htejun@gmail.com>
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To: Matthew Wilcox <matthew@wil.cx>
CC: linux-pci@atrey.karlin.mff.cuni.cz, Greg KH <greg@kroah.com>,
       lkml <linux-kernel@vger.kernel.org>
Subject: Re: question regarding cacheline size
References: <44FFD8C6.8080802@gmail.com> <20060907111120.GL2558@parisc-linux.org>
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Matthew Wilcox wrote:
> Just call pci_set_mwi(), that'll make sure the cache line size is set
> correctly.

Sounds simple enough.  Just two small worries though.

* It has an apparent side effect of setting PCI_COMMAND_INVALIDATE, 
which should be okay in sil3124's case.

* The controller might have some restrictions on configurable cache line 
size.  This is the same for MWI, so I guess this problem is just imaginary.

For the time being, I'll go with pci_set_mwi() but IMHO it would be 
better to have a pci helper for this purpose - 
pci_config_cacheline_size() or something.

Thanks.

-- 
tejun
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