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([2600:1700:dfe0:49f0:549a:788d:4851:c1b0]) by smtp.gmail.com with ESMTPSA id z3sm10684023otq.22.2020.12.30.08.15.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Dec 2020 08:15:58 -0800 (PST) Subject: Re: Registering IRQ for MT7530 internal PHYs To: Heiner Kallweit , DENG Qingfang Cc: "David S. Miller" , Andrew Lunn , Jakub Kicinski , Landen Chao , Marc Zyngier , Matthias Brugger , Philipp Zabel , Russell King , Sean Wang , Thomas Gleixner , Vivien Didelot , Vladimir Oltean , linux-kernel@vger.kernel.org, netdev , Weijie Gao , Chuanhong Guo , Linus Walleij , =?UTF-8?Q?Ren=c3=a9_van_Dorst?= References: <20201230042208.8997-1-dqfext@gmail.com> From: Florian Fainelli Message-ID: <546a8430-8865-1be8-4561-6681c7fa8ef8@gmail.com> Date: Wed, 30 Dec 2020 08:15:54 -0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Firefox/78.0 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/30/2020 1:12 AM, Heiner Kallweit wrote: > On 30.12.2020 10:07, DENG Qingfang wrote: >> Hi Heiner, >> Thanks for your reply. >> >> On Wed, Dec 30, 2020 at 3:39 PM Heiner Kallweit wrote: >>> I don't think that's the best option. >> >> I'm well aware of that. >> >>> You may want to add a PHY driver for your chip. Supposedly it >>> supports at least PHY suspend/resume. You can use the RTL8366RB >>> PHY driver as template. >> >> There's no MediaTek PHY driver yet. Do we really need a new one just >> for the interrupts? >> > Not only for the interrupts. The genphy driver e.g. doesn't support > PHY suspend/resume. And the PHY driver needs basically no code, > just set the proper callbacks. That statement about not supporting suspend/resume is not exactly true, the generic "1g" PHY driver only implements suspend/resume through the use of the standard BMCR power down bit, but not anything more complicated than that. Interrupt handling within the PHY itself is not defined by the existing standard registers and will typically not reside in a standard register space either, so just for that reason you do need a custom PHY driver. There are other advantages if you need to expose additional PHY features down the road like PHY counters, energy detection, automatic power down etc. I don't believe we will see discrete/standalone Mediatek PHY chips, but if that happens, then you would already have a framework for supporting them. -- Florian