Received: by 2002:a05:6a10:f347:0:0:0:0 with SMTP id d7csp14227623pxu; Mon, 4 Jan 2021 17:03:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJyoy7BWFuW7kRXAQJoktrv9YKpJw/hED/VTkqQVzlj+LNc8hFSwj6SPxqj2v5cs7m6WEX/r X-Received: by 2002:a17:906:edb2:: with SMTP id sa18mr65979891ejb.264.1609808630797; Mon, 04 Jan 2021 17:03:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609808630; cv=none; d=google.com; s=arc-20160816; b=juanTVu5d5y0wAbOPpj32nrmtn9B9GOiKnSVj0HRzk83jXSjiC3AnT3kNlXZ5f282n cpSBjvuWyKx7jydOS3QH1Xrh62/dy9YSMgKdlac8RP77rJUjm/1E7K20sbFLZ0DADc0T FQ4k96sv3YAk7wEYtGjm6+9zoFJNqeZr8jAxqOKJRm3/AU+jTW77buZmZ0eZi5Jf85SV RyO5C/49FHN4AJ0FEQs1pVu9aeG3KK4UE9HiHFWutWQ1IAFTujTcWjlwo1HaTssxMAwh G5p/e9dRkEDdNCGZmTKYqVT/CI/aq9nQt5GS25ulQINB2+XAWMYRJDIcQv6AaFLdol7W S/mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:ironport-sdr:ironport-sdr; bh=vPWAUInay0q1VRQWwHSCMF8rH9zKItWfkvtDZdN3GUw=; b=JaX8Yi/FPnnSu+CXNFLqjm98oVQ5rhA7i7YrJ6sgEREVana7FCFCBUo1qe9DfNqLly Qti2cMoyp7/T9+f3qsgoNqoorg/7N6nEXXAVFnyifTBYNSBxLbj7yuEumAGMqWR0Hi1V fMkOwGxRzogLiukoaoOW9At2/jMmqairxAOEeujLFQl8xnBv76dsDgvw6EHhzVbNpzjt zdCFHZ3nED0f3n1DYuyNQs9l+z2Jp/UTQRjJcA/P4tIhBd6AZKMXoglbK3y9J9ilszIp M6fAikljsPGMNfeHgNz2F2OEIXjUzdIfPLdnhLWHH4WQ1KjWffUWA3Dro458mwpGks2X Wkig== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id f21si32893226edr.152.2021.01.04.17.03.27; Mon, 04 Jan 2021 17:03:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726258AbhAEBAz (ORCPT + 99 others); Mon, 4 Jan 2021 20:00:55 -0500 Received: from mga05.intel.com ([192.55.52.43]:29970 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728135AbhAEBAy (ORCPT ); Mon, 4 Jan 2021 20:00:54 -0500 IronPort-SDR: ZjN6Bd0id77d2OGPho41pF5i6oI0xZbfuDCGNHHO5duXUfc1eN+K6EUf4/Yu22HiXgzfvMoDd9 ULhwHgKEGK+Q== X-IronPort-AV: E=McAfee;i="6000,8403,9854"; a="261794074" X-IronPort-AV: E=Sophos;i="5.78,475,1599548400"; d="scan'208";a="261794074" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2021 17:00:10 -0800 IronPort-SDR: YKBJ4G9TtzbPRZRopnJe6cy/fpFVC9NztFIfnfwdYurmNqsLzI35X91TkApaTHHZ1GTa+zWiLb wC9/JZ64qu5g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,475,1599548400"; d="scan'208";a="569540102" Received: from jsia-hp-z620-workstation.png.intel.com ([10.221.118.135]) by fmsmga005.fm.intel.com with ESMTP; 04 Jan 2021 17:00:08 -0800 From: Sia Jee Heng To: vkoul@kernel.org, Eugeniy.Paltsev@synopsys.com, robh+dt@kernel.org Cc: andriy.shevchenko@linux.intel.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac Date: Tue, 5 Jan 2021 08:42:51 +0800 Message-Id: <20210105004306.13588-2-jee.heng.sia@intel.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210105004306.13588-1-jee.heng.sia@intel.com> References: <20210105004306.13588-1-jee.heng.sia@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org YAML schemas Device Tree (DT) binding is the new format for DT to replace the old format. Introduce YAML schemas DT binding for dw-axi-dmac and remove the old version. Signed-off-by: Sia Jee Heng Reviewed-by: Rob Herring --- .../bindings/dma/snps,dw-axi-dmac.txt | 39 ------ .../bindings/dma/snps,dw-axi-dmac.yaml | 121 ++++++++++++++++++ 2 files changed, 121 insertions(+), 39 deletions(-) delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt deleted file mode 100644 index dbe160400adc..000000000000 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt +++ /dev/null @@ -1,39 +0,0 @@ -Synopsys DesignWare AXI DMA Controller - -Required properties: -- compatible: "snps,axi-dma-1.01a" -- reg: Address range of the DMAC registers. This should include - all of the per-channel registers. -- interrupt: Should contain the DMAC interrupt number. -- dma-channels: Number of channels supported by hardware. -- snps,dma-masters: Number of AXI masters supported by the hardware. -- snps,data-width: Maximum AXI data width supported by hardware. - (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits) -- snps,priority: Priority of channel. Array size is equal to the number of - dma-channels. Priority value must be programmed within [0:dma-channels-1] - range. (0 - minimum priority) -- snps,block-size: Maximum block size supported by the controller channel. - Array size is equal to the number of dma-channels. - -Optional properties: -- snps,axi-max-burst-len: Restrict master AXI burst length by value specified - in this property. If this property is missing the maximum AXI burst length - supported by DMAC is used. [1:256] - -Example: - -dmac: dma-controller@80000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x80000 0x400>; - clocks = <&core_clk>, <&cfgr_clk>; - clock-names = "core-clk", "cfgr-clk"; - interrupt-parent = <&intc>; - interrupts = <27>; - - dma-channels = <4>; - snps,dma-masters = <2>; - snps,data-width = <3>; - snps,block-size = <4096 4096 4096 4096>; - snps,priority = <0 1 2 3>; - snps,axi-max-burst-len = <16>; -}; diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml new file mode 100644 index 000000000000..3d2515463d56 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare AXI DMA Controller + +maintainers: + - Eugeniy Paltsev + +description: + Synopsys DesignWare AXI DMA Controller DT Binding + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + enum: + - snps,axi-dma-1.01a + + reg: + items: + - description: Address range of the DMAC registers + + reg-names: + items: + - const: axidma_ctrl_regs + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: Module Clock + + clock-names: + items: + - const: core-clk + - const: cfgr-clk + + '#dma-cells': + const: 1 + + dma-channels: + minimum: 1 + maximum: 8 + + snps,dma-masters: + description: | + Number of AXI masters supported by the hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + + snps,data-width: + description: | + AXI data width supported by hardware. + (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6] + + snps,priority: + description: | + Channel priority specifier associated with the DMA channels. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + + snps,block-size: + description: | + Channel block size specifier associated with the DMA channels. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + + snps,axi-max-burst-len: + description: | + Restrict master AXI burst length by value specified in this property. + If this property is missing the maximum AXI burst length supported by + DMAC is used. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 256 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - '#dma-cells' + - dma-channels + - snps,dma-masters + - snps,data-width + - snps,priority + - snps,block-size + +additionalProperties: false + +examples: + - | + #include + #include + /* example with snps,dw-axi-dmac */ + dmac: dma-controller@80000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x80000 0x400>; + clocks = <&core_clk>, <&cfgr_clk>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = <27>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <2>; + snps,data-width = <3>; + snps,block-size = <4096 4096 4096 4096>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; + }; -- 2.18.0