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Wed, 06 Jan 2021 19:00:44 -0800 (PST) MIME-Version: 1.0 References: <1608642587-15634-1-git-send-email-weiyi.lu@mediatek.com> <1608642587-15634-11-git-send-email-weiyi.lu@mediatek.com> <1609929721.7491.3.camel@mtksdaap41> <1609931196.30620.3.camel@mtksdaap41> In-Reply-To: <1609931196.30620.3.camel@mtksdaap41> From: Ikjoon Jang Date: Thu, 7 Jan 2021 11:00:32 +0800 Message-ID: Subject: Re: [PATCH v6 10/22] clk: mediatek: Add MT8192 basic clocks support To: Weiyi Lu Cc: Rob Herring , Nicolas Boichat , srv_heupstream , Stephen Boyd , open list , Project_Global_Chrome_Upstream_Group@mediatek.com, "moderated list:ARM/Mediatek SoC support" , Matthias Brugger , linux-clk@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jan 6, 2021 at 7:06 PM Weiyi Lu wrote: > > On Wed, 2021-01-06 at 18:52 +0800, Ikjoon Jang wrote: > > On Wed, Jan 6, 2021 at 6:42 PM Weiyi Lu wrote: > > > > > > On Wed, 2021-01-06 at 18:25 +0800, Ikjoon Jang wrote: > > > > On Tue, Dec 22, 2020 at 9:14 PM Weiyi Lu wrote: > > > > > > > > > > Add MT8192 basic clock providers, include topckgen, apmixedsys, > > > > > infracfg and pericfg. > > > > > > > > > > Signed-off-by: Weiyi Lu > > > > > --- > > > > > drivers/clk/mediatek/Kconfig | 8 + > > > > > drivers/clk/mediatek/Makefile | 1 + > > > > > drivers/clk/mediatek/clk-mt8192.c | 1326 +++++++++++++++++++++++++++++++++++++ > > > > > drivers/clk/mediatek/clk-mux.h | 15 + > > > > > 4 files changed, 1350 insertions(+) > > > > > create mode 100644 drivers/clk/mediatek/clk-mt8192.c > > > > > > > > > > > > > > > > > > > > > > diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h > > > > > index f5625f4..afbc7df 100644 > > > > > --- a/drivers/clk/mediatek/clk-mux.h > > > > > +++ b/drivers/clk/mediatek/clk-mux.h > > > > > @@ -77,6 +77,21 @@ struct mtk_mux { > > > > > _width, _gate, _upd_ofs, _upd, \ > > > > > CLK_SET_RATE_PARENT) > > > > > > > > > > +#define MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ > > > > > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > > > > > + _upd_ofs, _upd, _flags) \ > > > > > + GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ > > > > > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > > > > > + 0, _upd_ofs, _upd, _flags, \ > > > > > + mtk_mux_clr_set_upd_ops) > > > > > + > > > > > +#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ > > > > > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ > > > > > + _upd_ofs, _upd) \ > > > > > + MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ > > > > > + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \ > > > > > + _width, _upd_ofs, _upd, CLK_SET_RATE_PARENT) > > > > > + > > > > > > > > conflicts, these macros are already existed in upstream. > > > > > > really? These two macros don't show up in 5.11-rc1 yet. > > > > yep, maybe this one: a3ae549917f1 "clk: mediatek: Add new clkmux register API" > > > > The new macros in this patch are for the clock MUX without gate control. > It's a little different from those mux macros with gate control in > a3ae549917f1 "clk: mediatek: Add new clkmux register API" > sorry, my bad. it's just a simple context conflict from > > > > > > > > struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, > > > > > struct regmap *regmap, > > > > > spinlock_t *lock); > > > > > -- your another patch, 2aeff9d8c8e "clk: mediatek: Make mtk_clk_register_mux() a static function" was applied before this series. > > > > > 1.8.1.1.dirty > > > > > _______________________________________________ > > > > > Linux-mediatek mailing list > > > > > Linux-mediatek@lists.infradead.org > > > > > http://lists.infradead.org/mailman/listinfo/linux-mediatek > > > > > > _______________________________________________ > > > Linux-mediatek mailing list > > > Linux-mediatek@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-mediatek >