Received: by 2002:a05:6a10:f347:0:0:0:0 with SMTP id d7csp270102pxu; Thu, 7 Jan 2021 04:44:10 -0800 (PST) X-Google-Smtp-Source: ABdhPJw/z8r5Z7M3lYoQG+wKyfG0mkAROJTHJMvNOXtElElC8tMJ7NId3aqb9jU2d3anOXJdjVIQ X-Received: by 2002:a05:6402:3048:: with SMTP id bu8mr1554224edb.49.1610023450577; Thu, 07 Jan 2021 04:44:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610023450; cv=none; d=google.com; s=arc-20160816; b=W8tLTz0XE5mzwS4N1mydjkqIMKWfl/UyTPi6nobzurCThLWyz1Fk73vJXXmOo0Ldgh Q6wjmhfzTITQKUG9FGD0XFgTlEDCavAI5xTuktdjj/znrVD0S9iR6tqHbO3ERAFL3RO3 Na0i33oIG4Nkv+expuwW3xuuIMm/KaqNEvu7AY6bPHTsKYp9phqi04jcnrOe8hXTIscz d+rxI2NWQpzeWc6H2K+kf4hJLwTC3JW0FAtAHzf0HnB9mgI0kKeZp56bVeOHwTAm+oLo GKhPD149z+m1AiYKmcGzHW1l0yO6T96HCFjD7rkwjo2+Nhzn3O0+3cjj9d+gKWwQl50m /T5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=2oR8vCKriNzEfsWqoaS9jCxTf9xoRixiySPrYpRjQkM=; b=gZ/D5AvLYNACcmKPaZLH6E019dl4YC3NVKW/aFRjD07S5fEGrBkxQQ9nywLOiNGd32 LOMzUROkzZFeCUj0oXMlzPSrsRxAbcDdMNkf9nczyFZ4RpDM92zAQzl3fXXYCg5lvAF/ /tvKAX0Jigbys6V6j9pNkqY0t4XMePVzbtI3lHWBFE4chEV0XzhbtcqRaAcvU5TddA62 +1i7DL+cBbvHnSxMaAzkd4ZMgS+7Ktsq/dCcYmptjJNfdJ9QDlB0ZqiJQfgE+HYINFWj kxcIYsLxzPULbJXBYuruuHnRGu+iO3pl4+8ow3DBUQZEed602EEOcjYwYkJQb1PH5ywT 2IKQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n5si2205676eda.301.2021.01.07.04.43.47; Thu, 07 Jan 2021 04:44:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728503AbhAGMlR (ORCPT + 99 others); Thu, 7 Jan 2021 07:41:17 -0500 Received: from foss.arm.com ([217.140.110.172]:59940 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728247AbhAGMlL (ORCPT ); Thu, 7 Jan 2021 07:41:11 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B06D61570; Thu, 7 Jan 2021 04:39:48 -0800 (PST) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4644A3F719; Thu, 7 Jan 2021 04:39:47 -0800 (PST) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, leo.yan@linaro.org, mike.leach@linaro.org, anshuman.khandual@arm.com, Jonathan Zhou , Catalin Marinas , Will Deacon , Suzuki K Poulose Subject: [PATCH v6 25/26] arm64: Add TRFCR_ELx definitions Date: Thu, 7 Jan 2021 12:38:58 +0000 Message-Id: <20210107123859.674252-26-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20210107123859.674252-1-suzuki.poulose@arm.com> References: <20210107123859.674252-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jonathan Zhou Add definitions for the Arm v8.4 SelfHosted trace extensions registers. Acked-by: Catalin Marinas Cc: Will Deacon Signed-off-by: Jonathan Zhou [ split the register definitions to separate patch rename some of the symbols ] Signed-off-by: Suzuki K Poulose --- arch/arm64/include/asm/sysreg.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 8b5e7e5c3cc8..4acff97519b9 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -191,6 +191,7 @@ #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) @@ -471,6 +472,7 @@ #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) +#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) @@ -829,6 +831,7 @@ #define ID_AA64MMFR2_CNP_SHIFT 0 /* id_aa64dfr0 */ +#define ID_AA64DFR0_TRACE_FILT_SHIFT 40 #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 #define ID_AA64DFR0_PMSVER_SHIFT 32 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 @@ -1003,6 +1006,14 @@ /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) +#define TRFCR_ELx_TS_SHIFT 5 +#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) +#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) +#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) +#define TRFCR_EL2_CX BIT(3) +#define TRFCR_ELx_ExTRE BIT(1) +#define TRFCR_ELx_E0TRE BIT(0) + #ifdef __ASSEMBLY__ .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 -- 2.24.1