Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
From:   Shradha Todi <shradha.t@samsung.com>
To:     linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-pci@vger.kernel.org
Cc:     pankaj.dubey@samsung.com, sriram.dash@samsung.com,
        niyas.ahmed@samsung.com, p.rajanbabu@samsung.com,
        l.mehra@samsung.com, hari.tv@samsung.com,
        Shradha Todi <shradha.t@samsung.com>,
        Rob Herring <robh+dt@kernel.org>,
        Thierry Reding <thierry.reding@gmail.com>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        Vidya Sagar <vidyas@nvidia.com>
Subject: [PATCH v7 5/5] arm64: tegra: Add support for ZRX DC PHY property
Date:   Thu,  7 Jan 2021 20:58:43 +0530
Message-Id: <1610033323-10560-6-git-send-email-shradha.t@samsung.com>
In-Reply-To: <1610033323-10560-1-git-send-email-shradha.t@samsung.com>
Content-Type: text/plain; charset="utf-8"
CMS-TYPE: 105P
References: <1610033323-10560-1-git-send-email-shradha.t@samsung.com>
        <CGME20210107153116epcas5p3510286e503e690537d5b2eb7486fa7ab@epcas5p3.samsung.com>
Precedence: bulk

DesignWare controller driver provides the support to handle the PHYs which
are compliant to ZRX-DC specification based on "phy-zrxdc-compliant" DT
property. So, add "phy-zrxdc-compliant" property in tegra PCIe PHY DT
nodes.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Shradha Todi <shradha.t@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Vidya Sagar <vidyas@nvidia.com>
To: devicetree@vger.kernel.org
To: linux-tegra@vger.kernel.org
---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 25f36d6..9d91006 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1006,6 +1006,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_1: phy@3e20000 {
@@ -1014,6 +1015,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_2: phy@3e30000 {
@@ -1022,6 +1024,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_3: phy@3e40000 {
@@ -1030,6 +1033,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_4: phy@3e50000 {
@@ -1038,6 +1042,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_5: phy@3e60000 {
@@ -1046,6 +1051,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_6: phy@3e70000 {
@@ -1054,6 +1060,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_7: phy@3e80000 {
@@ -1062,6 +1069,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_8: phy@3e90000 {
@@ -1070,6 +1078,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_9: phy@3ea0000 {
@@ -1078,6 +1087,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_0: phy@3eb0000 {
@@ -1086,6 +1096,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_1: phy@3ec0000 {
@@ -1094,6 +1105,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_2: phy@3ed0000 {
@@ -1102,6 +1114,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_3: phy@3ee0000 {
@@ -1110,6 +1123,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_4: phy@3ef0000 {
@@ -1118,6 +1132,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_5: phy@3f00000 {
@@ -1126,6 +1141,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_6: phy@3f10000 {
@@ -1134,6 +1150,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_7: phy@3f20000 {
@@ -1142,6 +1159,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_10: phy@3f30000 {
@@ -1150,6 +1168,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_11: phy@3f40000 {
@@ -1158,6 +1177,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		hsp_aon: hsp@c150000 {
-- 
2.7.4