Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Date:   Mon, 11 Jan 2021 16:41:38 +0800
From:   Leo Yan <leo.yan@linaro.org>
To:     Namhyung Kim <namhyung@kernel.org>
Cc:     Arnaldo Carvalho de Melo <acme@kernel.org>,
        Jiri Olsa <jolsa@redhat.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@redhat.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Andi Kleen <ak@linux.intel.com>,
        Ian Rogers <irogers@google.com>,
        Kan Liang <kan.liang@linux.intel.com>,
        Joe Mario <jmario@redhat.com>, David Ahern <dsahern@gmail.com>,
        Don Zickus <dzickus@redhat.com>, Al Grant <Al.Grant@arm.com>,
        James Clark <james.clark@arm.com>,
        linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 03/11] perf c2c: Add dimensions for load miss
Message-ID: <20210111084138.GE3241@leoy-ThinkPad-X240s>
References: <20201213133850.10070-1-leo.yan@linaro.org>
 <20201213133850.10070-4-leo.yan@linaro.org>
 <CAM9d7cjOkSZRZz6JJW-eCD0Dx5E6rGzfmvU3deQyEr2RLUgzGA@mail.gmail.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <CAM9d7cjOkSZRZz6JJW-eCD0Dx5E6rGzfmvU3deQyEr2RLUgzGA@mail.gmail.com>
Precedence: bulk

On Wed, Jan 06, 2021 at 04:42:59PM +0900, Namhyung Kim wrote:
> On Sun, Dec 13, 2020 at 10:39 PM Leo Yan <leo.yan@linaro.org> wrote:
> >
> > Add dimensions for load miss and its percentage calculation, which is to
> > be displayed in the single cache line output.
> >
> > Signed-off-by: Leo Yan <leo.yan@linaro.org>
> > ---
> >  tools/perf/builtin-c2c.c | 107 +++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 107 insertions(+)
> >
> > diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
> > index 00014e3d81fa..27745340c14a 100644
> > --- a/tools/perf/builtin-c2c.c
> > +++ b/tools/perf/builtin-c2c.c
> > @@ -624,6 +624,10 @@ tot_hitm_cmp(struct perf_hpp_fmt *fmt __maybe_unused,
> >          (stats)->rmt_hitm +            \
> >          (stats)->rmt_hit)
> >
> > +#define TOT_LD_MISS(stats)             \
> > +       ((stats)->lcl_dram +            \
> > +        (stats)->rmt_dram)
> > +
> 
> Is this true always?  I'm not sure if there's a case where stores can go to DRAM
> directly.. maybe like a kind of uncached accesses.

Firstly, from my understanding, the uncached accesses are not accounted
in the "load miss" metrics.  You could see there have other two metrics
"stats->st_uncache" and "stats->ld_uncache" which present the store
uncached and load uncached respectively.

Furthermore, based on the function total_records(), it uses below
formula to account the total load accesses:

        lclmiss  = stats->lcl_dram +
                   stats->rmt_dram +
                   stats->rmt_hitm +
                   stats->rmt_hit;

        ldcnt    = lclmiss +
                   stats->ld_fbhit +
                   stats->ld_l1hit +
                   stats->ld_l2hit +
                   stats->ld_llchit +
                   stats->lcl_hitm;

So this patch series classifies these metrics into two numbers: load hit
and load miss; load hit is considered as hit at any cache levels
(L1, L2, LLC and even remote cache), the load miss is accounted with the
rest metrics (lcl_dram + rmt_dram).

> Also it can be a static function..

Yeah, will fix.

Thanks,
Leo