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Mon, 11 Jan 2021 08:54:03 +0000 Subject: Re: [PATCH] amdgpu: Avoid sleeping during FPU critical sections To: Jeremy Cline , Harry Wentland , Leo Li Cc: Alex Deucher , David Airlie , Daniel Vetter , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Timothy Pearson References: <20210108215838.470637-1-jcline@redhat.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= Message-ID: <3c94f9d6-501d-271c-ca83-1cf4229cb3ab@amd.com> Date: Mon, 11 Jan 2021 09:53:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 In-Reply-To: <20210108215838.470637-1-jcline@redhat.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [2a02:908:1252:fb60:be8a:bd56:1f94:86e7] X-ClientProxiedBy: AM8P191CA0017.EURP191.PROD.OUTLOOK.COM (2603:10a6:20b:21a::22) To MN2PR12MB3775.namprd12.prod.outlook.com (2603:10b6:208:159::19) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [IPv6:2a02:908:1252:fb60:be8a:bd56:1f94:86e7] (2a02:908:1252:fb60:be8a:bd56:1f94:86e7) by AM8P191CA0017.EURP191.PROD.OUTLOOK.COM (2603:10a6:20b:21a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3742.6 via Frontend Transport; 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Narrow the scope to just these two parts to > avoid sleeping while using the FPU. > > Fixes: 7a8a3430be15 ("amdgpu: Wrap FPU dependent functions in dc20") > Cc: Timothy Pearson > Signed-off-by: Jeremy Cline Good catch, but I would rather replace the kzalloc(GFP_KERNEL) with a kzalloc(GFP_ATOMIC) for now. We have tons of problems with this DC_FP_START()/DC_FP_END() annotations and are even in the process of moving them out of the file because the compiles tend to clutter FP registers even outside of the annotated ranges on some architectures. Regards, Christian. > --- > drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c > index e04ecf0fc0db..a4fa5bf016c1 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c > @@ -3622,6 +3622,7 @@ static bool init_soc_bounding_box(struct dc *dc, > if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { > int i; > > + DC_FP_START(); > dcn2_0_nv12_soc.sr_exit_time_us = > fixed16_to_double_to_cpu(bb->sr_exit_time_us); > dcn2_0_nv12_soc.sr_enter_plus_exit_time_us = > @@ -3721,6 +3722,7 @@ static bool init_soc_bounding_box(struct dc *dc, > dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts = > fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts); > } > + DC_FP_END(); > } > > if (pool->base.pp_smu) { > @@ -3777,8 +3779,6 @@ static bool dcn20_resource_construct( > enum dml_project dml_project_version = > get_dml_project_version(ctx->asic_id.hw_internal_rev); > > - DC_FP_START(); > - > ctx->dc_bios->regs = &bios_regs; > pool->base.funcs = &dcn20_res_pool_funcs; > > @@ -3959,8 +3959,10 @@ static bool dcn20_resource_construct( > ranges.reader_wm_sets[i].wm_inst = i; > ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; > ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; > + DC_FP_START(); > ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; > ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; > + DC_FP_END(); > > ranges.num_reader_wm_sets = i + 1; > } > @@ -4125,12 +4127,10 @@ static bool dcn20_resource_construct( > pool->base.oem_device = NULL; > } > > - DC_FP_END(); > return true; > > create_fail: > > - DC_FP_END(); > dcn20_resource_destruct(pool); > > return false;