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Otherwise, there will be hole of 32 bytes with each memblock allocation if it is requested to be aligned with SMP_CACHE_BYTES. Reviewed-by: Anup Patel Tested-by: Geert Uytterhoeven (on vexriscv) Signed-off-by: Atish Patra --- arch/riscv/include/asm/cache.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index 9b58b104559e..c9c669ea2fe6 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -7,7 +7,11 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +#ifdef CONFIG_64BIT #define L1_CACHE_SHIFT 6 +#else +#define L1_CACHE_SHIFT 5 +#endif #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -- 2.25.1