From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Segher Boessenkool <segher@kernel.crashing.org>
Subject: Re: Opinion on ordering of writel vs. stores to RAM
Date: Mon, 11 Sep 2006 11:12:29 -0700
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On Sunday, September 10, 2006 5:54 pm, Segher Boessenkool wrote:
> >>  - writel/readl become totally ordered (including vs. memory).
> >> Basically x86-like. Expensive (very expensive even on some
> >> architectures) but also very safe.
> >
> > This approach will minimize driver changes, and would imply the
> > removal
> > of some existing mmiowb() and wmb() macros.
>
> Like I tried to explain already, in my competing approach, no drivers
> would need changes either.  And you could remove those macro's (or
> their more-verbosely-saying-what-their-doing, preferably bus-specific
> as well) as well -- but you'll face the wrath of those who care about
> performance of those drivers on non-x86 platforms.

Right, at the cost of more complexity in the accessor routines.

> Hence my proposal of calling it pci_cpu_to_cpu_barrier() -- what it
> orders is accesses from separate CPUs.  Oh, and it's bus-specific,
> of course.

Makes sense to me, I have no problem with that name since it's really intended 
to order posted PCI writes from different CPUs.

Jesse
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