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From:   =?UTF-8?B?6Zmz5bu65a6P?= <reniuschengl@gmail.com>
Date:   Thu, 14 Jan 2021 14:24:49 +0800
Message-ID: <CAJU4x8uKHQy_hbMhsErzWb2U5USjMRhAZv=+14a9zDn068vHmw@mail.gmail.com>
Subject: Re: [PATCH] mmc: sdhci-pci-gli: Enlarge ASPM L1 entry delay of GL9763E
To:     Ulf Hansson <ulf.hansson@linaro.org>
Cc:     Adrian Hunter <adrian.hunter@intel.com>,
        "linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Ben Chuang <ben.chuang@genesyslogic.com.tw>,
        greg.tu@genesyslogic.com.tw
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> Ulf Hansson <ulf.hansson@linaro.org> =E6=96=BC 2021=E5=B9=B41=E6=9C=8813=
=E6=97=A5 =E9=80=B1=E4=B8=89 =E4=B8=8B=E5=8D=886:53=E5=AF=AB=E9=81=93=EF=BC=
=9A
>
> On Wed, 6 Jan 2021 at 10:27, Renius Chen <reniuschengl@gmail.com> wrote:
> >
> > The R/W performance of GL9763E is low with some platforms, which
> > support ASPM mechanism, due to entering L1 state very frequently
> > in R/W process. Enlarge its ASPM L1 entry delay to improve the
> > R/W performance of GL9763E.
>
> What do you mean by frequently? In between a burst of request or
> during a burst of request?

GL9763E enters ASPM L1 state after a very short idle in default, even
during a burst of request.

> I am thinking that this could have an effect on energy instead, but I
> guess it's not always straightforward to decide what's most important.
>
> Anyway, what does it mean when you change to use 0x3FF? Are you
> increasing the idle period? Then for how long?

Yes, we considered that having high performance is more important than
saving power during a burst of request.
So we increased the idle period for 260us, by setting 0x3FF to the
ASPM L1 entry delay bits of our vendor-specific register.
Anyway, GL9763E can still enter ASPM L1 state by a longer idle.

Thanks for reviewing.

Best regards,
Renius

> Kind regards
> Uffe
>
> >
> > Signed-off-by: Renius Chen <reniuschengl@gmail.com>
> > ---
> >  drivers/mmc/host/sdhci-pci-gli.c | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-=
pci-gli.c
> > index c6a107d7c742..2d13bfcbcacf 100644
> > --- a/drivers/mmc/host/sdhci-pci-gli.c
> > +++ b/drivers/mmc/host/sdhci-pci-gli.c
> > @@ -88,6 +88,10 @@
> >  #define PCIE_GLI_9763E_SCR      0x8E0
> >  #define   GLI_9763E_SCR_AXI_REQ           BIT(9)
> >
> > +#define PCIE_GLI_9763E_CFG2      0x8A4
> > +#define   GLI_9763E_CFG2_L1DLY    GENMASK(28, 19)
> > +#define   GLI_9763E_CFG2_L1DLY_MAX 0x3FF
> > +
> >  #define PCIE_GLI_9763E_MMC_CTRL  0x960
> >  #define   GLI_9763E_HS400_SLOW     BIT(3)
> >
> > @@ -792,6 +796,11 @@ static void gli_set_gl9763e(struct sdhci_pci_slot =
*slot)
> >         value &=3D ~GLI_9763E_HS400_SLOW;
> >         pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
> >
> > +       pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
> > +       value &=3D ~GLI_9763E_CFG2_L1DLY;
> > +       value |=3D FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DL=
Y_MAX);
> > +       pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
> > +
> >         pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
> >         value &=3D ~GLI_9763E_VHS_REV;
> >         value |=3D FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
> > --
> > 2.27.0
> >