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From:   Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Date:   Thu, 14 Jan 2021 15:44:05 -0700
Message-ID: <CAOCk7NqJ7=Rpwzx9ZQ9p=YHrxYeE69YphRq3BbzFwK_TyiVGFA@mail.gmail.com>
Subject: Re: [PATCH 1/9] clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clock
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@somainline.org>
Cc:     MSM <linux-arm-msm@vger.kernel.org>, konrad.dybcio@somainline.org,
        marijn.suijten@somainline.org, martin.botka@somainline.org,
        phone-devel@vger.kernel.org, lkml <linux-kernel@vger.kernel.org>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>, linux-clk@vger.kernel.org,
        DTML <devicetree@vger.kernel.org>
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On Thu, Jan 14, 2021 at 3:40 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org> wrote:
>
> Il 14/01/21 23:33, Jeffrey Hugo ha scritto:
> > On Thu, Jan 14, 2021 at 3:13 PM AngeloGioacchino Del Regno
> > <angelogioacchino.delregno@somainline.org> wrote:
> >>
> >> Il 14/01/21 23:12, Jeffrey Hugo ha scritto:
> >>> On Sat, Jan 9, 2021 at 6:47 AM AngeloGioacchino Del Regno
> >>> <angelogioacchino.delregno@somainline.org> wrote:
> >>>>
> >>>> This clock enables the GPLL0 output to the multimedia subsystem
> >>>> clock controller.
> >>>>
> >>>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> >>>
> >>> Any reason why you are not also adding the div_clk?
> >>>
> >>
> >> Yes, just one: I haven't tested it... and my devices worked without.
> >> Perhaps we can add it whenever we find out if something really needs it?
> >
> > I'm mildly surprised you need to turn on the gate to the PLL0 out, but
> > not the div_out.  The div_out/div_clk is also fed into every RCG that
> > exists in the MMCC.
> >
> > Per the frequency plan the following RCGs require it -
> >
> > cci
> > cpp
> > fd_core
> > camss_gp[0-1]
> > jpeg0
> > mclk[0-3]
> > csi[0-2]phytimer
> > dp_gtc
> > maxi
> > axi
> > ahb
> >
> > Also, I'm very interested in all things 8998, and would generally
> > appreciate being added to the to: list.
> >
>
> To be honest, I was surprised as well because.. yes, I know that these
> RCGs seem to need it, but then their clock tables don't contain any
> reference to the gpll0 divider, hence it's never getting used - and that
> works great, for now.
>
> I am aware of the fact that the clocks that you've mentioned are using
> the divider to reduce jitter, but I haven't done any camera test on my
> devices yet: that's definitely in my plans and I really can't wait to do
> that (as I successfully did for SDM630/660), but... we have more than
> 100 patches in our trees.
> We need to get upstream in the same working order as what we have here,
> so that we don't diverge that much and our work is kept in a
> maintainable state (avoiding to lose pieces around).
>
> I'm sure that I'll send a commit adding the gpll0 divider branch as soon
> as I will start the camera work: I feel it, it's going to give me issues
> without, in that field.
>
> By the way, noted. I'll make sure to add you in the to/cc for all of the
> next series regarding 8998 that I'll send.
>
> Meanwhile, you may want to check out all the recent patches that I've
> sent, as like 90% are MSM8998-centric... :))

I noticed, and I'm excited to see additional work since I've had a
lack of spare time, although I think you've monopolized my backlog  :)