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From:   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To:     gustavo.pimentel@synopsys.com, bhelgaas@google.com,
        Vidya Sagar <vidyas@nvidia.com>, amurray@thegoodpenguin.co.uk,
        robh@kernel.org, jingoohan1@gmail.com, jonathanh@nvidia.com,
        treding@nvidia.com
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, kthota@nvidia.com,
        mmaddireddy@nvidia.com, linux-pci@vger.kernel.org,
        linux-kernel@vger.kernel.org, sagar.tv@gmail.com
Subject: Re: [PATCH V3] PCI: dwc: Add support to configure for ECRC
Date:   Fri, 15 Jan 2021 12:17:00 +0000
Message-Id: <161071299508.16820.14705114114590810176.b4-ty@arm.com>
In-Reply-To: <20201230165723.673-1-vidyas@nvidia.com>
References: <20201230165723.673-1-vidyas@nvidia.com>
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On Wed, 30 Dec 2020 22:27:23 +0530, Vidya Sagar wrote:
> DesignWare core has a TLP digest (TD) override bit in one of the control
> registers of ATU. This bit also needs to be programmed for proper ECRC
> functionality. This is currently identified as an issue with DesignWare
> IP version 4.90a.

Applied to pci/dwc, thanks!

[1/1] PCI: dwc: Add support to configure for ECRC
      https://git.kernel.org/lpieralisi/pci/c/9b3a84d0f5

Thanks,
Lorenzo