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Fri, 15 Jan 2021 12:19:30 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Paolo Bonzini Cc: Alexander Graf , Atish Patra , Alistair Francis , Damien Le Moal , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v16 03/17] RISC-V: KVM: Implement VCPU create, init and destroy functions Date: Fri, 15 Jan 2021 17:48:32 +0530 Message-Id: <20210115121846.114528-4-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115121846.114528-1-anup.patel@wdc.com> References: <20210115121846.114528-1-anup.patel@wdc.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [122.167.152.18] X-ClientProxiedBy: MAXPR0101CA0024.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:c::34) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.167.152.18) by MAXPR0101CA0024.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:c::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3763.10 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?7R5yVoikJ/mDN26ajly13lotiovwnV0xAeOsfZ0cPdDuThLsyqoMjWIZwl4V?= =?us-ascii?Q?upEID3u/WQ/qFvwPr4fJd9rwS0eONZRe2ef1EkQl8uwQxA5J0RZxxkphbAHF?= =?us-ascii?Q?crtn/bYaTmRXseLvV7TMzRbnG+O2fnn2MwJafU4PrCmj2uJkFiLrBp92tIDS?= =?us-ascii?Q?iXi7sqhVAV9Ho3hH1Un3McmBw+0E0j5NXr2zX7qpMmk/LfqZZv761wtEjAI4?= =?us-ascii?Q?Bvyv70E9VCQEFk95dSExCnDnKFxWwwCR50xaRlcADJWrHHNR5Yv1lPq6mLXq?= =?us-ascii?Q?miHORIXqsDtTQ1JpVOkOEgQ3y2v5thGWxoeuCKYcG11Gf3Q6gHaG1xwbkQvK?= =?us-ascii?Q?ciO41u7nE1lXOdVLHUHPoWNj3h1X2cdKQ/l/moZlOqXEK+8hz+4ZsjpwGuEk?= =?us-ascii?Q?Z/TkmfFlc2t0GCLa272vrOd7sEgZcip9QcLSgmGrXIVLmISHW58tc6oIWGgS?= =?us-ascii?Q?Ic+jBjAsWpT7qv+9xlyD/w2vtih6BxidvprcTG+aC0x7GOmE4mLxB5MHcTeF?= =?us-ascii?Q?ghUc8okaoJnyqQBoi6vmFoIS2PiU4/Lu/STl5dcoeNyCbWO+YBj7AU776pC+?= =?us-ascii?Q?ebXp/Efe0sdWkfKmI43a+SgUViFuzzX1ACi3P7GWTccsGgIZbdFyYItdkuJU?= =?us-ascii?Q?KV535fTKu1wU3YdpkNoOAroojznk3rwKmCsSQacyxoXAOby4ujuhlSsBE1BY?= =?us-ascii?Q?chuORKICdjl1iws3q9b7bwJUruHvLRV7TuRzdFknZ1jmBz75gpu6Oqmoq7dd?= =?us-ascii?Q?zPP7ZRQqQUz0B7lwTmQt1PMdpmpwZFzgP/YnjAi3Cz6ccpG9xHeOnp4PWX/S?= =?us-ascii?Q?egdhM5TuH6beI/ehvdNamUOe+0BMSSOn+XvyVRLr2iiM135MGSOFiWzFCZbD?= =?us-ascii?Q?iFhtpNF4mulbalAZeVEMhdMuPUZCUAIgXe+jZoFilipQEWPZE9mNUAcL+y2k?= =?us-ascii?Q?mDrek6/9pkBoSqvz+zpOHkAYA4tKcIirHWTFWKi0G1UZfcdFammC+SPvzmjG?= =?us-ascii?Q?9m2x?= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: db2846bf-50aa-4b97-7223-08d8b94fcf3c X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jan 2021 12:19:30.7882 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: MmiNzr8+RffX67AGdBhM8+yfPpocRMe2YvKVKExEJn2KN3Roeuv4D1R2TEejPiJtWzjuSHtjORX+vmlKrR9qyA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB3769 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch implements VCPU create, init and destroy functions required by generic KVM module. We don't have much dynamic resources in struct kvm_vcpu_arch so these functions are quite simple for KVM RISC-V. Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini Reviewed-by: Alexander Graf --- arch/riscv/include/asm/kvm_host.h | 69 +++++++++++++++++++++++++++++++ arch/riscv/kvm/vcpu.c | 55 ++++++++++++++++++++---- 2 files changed, 115 insertions(+), 9 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index fdd63bafb714..43e85523a07e 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -63,7 +63,76 @@ struct kvm_cpu_trap { unsigned long htinst; }; +struct kvm_cpu_context { + unsigned long zero; + unsigned long ra; + unsigned long sp; + unsigned long gp; + unsigned long tp; + unsigned long t0; + unsigned long t1; + unsigned long t2; + unsigned long s0; + unsigned long s1; + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; + unsigned long a4; + unsigned long a5; + unsigned long a6; + unsigned long a7; + unsigned long s2; + unsigned long s3; + unsigned long s4; + unsigned long s5; + unsigned long s6; + unsigned long s7; + unsigned long s8; + unsigned long s9; + unsigned long s10; + unsigned long s11; + unsigned long t3; + unsigned long t4; + unsigned long t5; + unsigned long t6; + unsigned long sepc; + unsigned long sstatus; + unsigned long hstatus; +}; + +struct kvm_vcpu_csr { + unsigned long vsstatus; + unsigned long hie; + unsigned long vstvec; + unsigned long vsscratch; + unsigned long vsepc; + unsigned long vscause; + unsigned long vstval; + unsigned long hvip; + unsigned long vsatp; + unsigned long scounteren; +}; + struct kvm_vcpu_arch { + /* VCPU ran atleast once */ + bool ran_atleast_once; + + /* ISA feature bits (similar to MISA) */ + unsigned long isa; + + /* CPU context of Guest VCPU */ + struct kvm_cpu_context guest_context; + + /* CPU CSR context of Guest VCPU */ + struct kvm_vcpu_csr guest_csr; + + /* CPU context upon Guest VCPU reset */ + struct kvm_cpu_context guest_reset_context; + + /* CPU CSR context upon Guest VCPU reset */ + struct kvm_vcpu_csr guest_reset_csr; + /* Don't run the VCPU (blocked) */ bool pause; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 8d8d140a0caf..84deeddbffbe 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -35,6 +35,27 @@ struct kvm_stats_debugfs_item debugfs_entries[] = { { NULL } }; +#define KVM_RISCV_ISA_ALLOWED (riscv_isa_extension_mask(a) | \ + riscv_isa_extension_mask(c) | \ + riscv_isa_extension_mask(d) | \ + riscv_isa_extension_mask(f) | \ + riscv_isa_extension_mask(i) | \ + riscv_isa_extension_mask(m) | \ + riscv_isa_extension_mask(s) | \ + riscv_isa_extension_mask(u)) + +static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + struct kvm_cpu_context *reset_cntx = &vcpu->arch.guest_reset_context; + + memcpy(csr, reset_csr, sizeof(*csr)); + + memcpy(cntx, reset_cntx, sizeof(*cntx)); +} + int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) { return 0; @@ -42,7 +63,25 @@ int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) { - /* TODO: */ + struct kvm_cpu_context *cntx; + + /* Mark this VCPU never ran */ + vcpu->arch.ran_atleast_once = false; + + /* Setup ISA features available to VCPU */ + vcpu->arch.isa = riscv_isa_extension_base(NULL) & KVM_RISCV_ISA_ALLOWED; + + /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */ + cntx = &vcpu->arch.guest_reset_context; + cntx->sstatus = SR_SPP | SR_SPIE; + cntx->hstatus = 0; + cntx->hstatus |= HSTATUS_VTW; + cntx->hstatus |= HSTATUS_SPVP; + cntx->hstatus |= HSTATUS_SPV; + + /* Reset VCPU */ + kvm_riscv_reset_vcpu(vcpu); + return 0; } @@ -55,15 +94,10 @@ void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) { } -int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) -{ - /* TODO: */ - return 0; -} - void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) { - /* TODO: */ + /* Flush the pages pre-allocated for Stage2 page table mappings */ + kvm_riscv_stage2_flush_cache(vcpu); } int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) @@ -209,6 +243,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) struct kvm_cpu_trap trap; struct kvm_run *run = vcpu->run; + /* Mark this VCPU ran at least once */ + vcpu->arch.ran_atleast_once = true; + vcpu->arch.srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); /* Process MMIO value returned from user-space */ @@ -282,7 +319,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) * get an interrupt between __kvm_riscv_switch_to() and * local_irq_enable() which can potentially change CSRs. */ - trap.sepc = 0; + trap.sepc = vcpu->arch.guest_context.sepc; trap.scause = csr_read(CSR_SCAUSE); trap.stval = csr_read(CSR_STVAL); trap.htval = csr_read(CSR_HTVAL); -- 2.25.1