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[23.128.96.18]) by mx.google.com with ESMTP id jt18si6776619ejb.633.2021.01.19.05.25.35; Tue, 19 Jan 2021 05:25:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=OeUsyJeQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392470AbhASNHy (ORCPT + 99 others); Tue, 19 Jan 2021 08:07:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2393007AbhASNAG (ORCPT ); Tue, 19 Jan 2021 08:00:06 -0500 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD323C0613D3 for ; Tue, 19 Jan 2021 04:52:08 -0800 (PST) Received: by mail-ed1-x532.google.com with SMTP id b2so21348749edm.3 for ; Tue, 19 Jan 2021 04:52:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Ejq4HtAQKiBD88tnqaXHBsdxX4bqHNk2H5bixMlEZ8E=; b=OeUsyJeQWOtd2isUYxRj908deHZQ708lk0IJ971sXNuOtMh4beAsyrqPQ1Rbx+yA7L 8P3ID2tH/j2ZzQicj3R4kVgUvBmRmleYRrhlHvceOWZ+tqAQsH+KA5fJBkSK05n1SE98 31VevdUV/TSuENiY4+uK4nORTYTelgpk1PcU0hMrvk8a83+U9I512yiJ6m+xCDEIeylh 58oUvufVYJ4Op6is0R5fRdy2rImKkg2I/1akzGa8ErVTa+OyATlW6vmm9ST71C5yxfLQ nZRfrWvtChY9I0dJVeuHnhZxaEp/Fo/nx6A1OHnCFRmoa8s9ioIbP1KabWJIpQSCjeYh YFJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Ejq4HtAQKiBD88tnqaXHBsdxX4bqHNk2H5bixMlEZ8E=; b=k9YCGD3FS3ivIs0FnER1yyw18QjYGFOzrfnDvGCpkbWbO/eVdFL06J81SQaPjkSVHA FWRPy/y6Chnq0IVuaOUD8Gq5gUwBDAQcneA5S6KFSNtiEvmVxz8cE0Q2cZzTGHSjyvsd iRkXNP9g513ZFnB9fjjb+NW6PFCbcXVIAYXjg/tntCzcOB0imjTt1jcA2lI6L3hF8c6l nIltEO6j1lmPLmBJvXvjO/otJnqqYOo8bBUdIwSGxNyz0W+n+Sj3fuhMXoBbdu7iynUj lAx9VCX+n5rNhUFPl6VYlbu74eqqM1ZT1+m3pOLDkmKyNursv7N3mZ+uyBKBh5j1bLV3 QqxQ== X-Gm-Message-State: AOAM530Hu+nkczFbeg74bbwvUVS5Hsic1wuvlXMh+kbFyzIdscpz0XMK OvMLA1D6kD3AG2w+1xIzc91D72RV5/8l7jGsCoS/4A== X-Received: by 2002:aa7:d401:: with SMTP id z1mr3244360edq.213.1611060727543; Tue, 19 Jan 2021 04:52:07 -0800 (PST) MIME-Version: 1.0 References: <20210112133010.21397-1-digetx@gmail.com> In-Reply-To: <20210112133010.21397-1-digetx@gmail.com> From: Bartosz Golaszewski Date: Tue, 19 Jan 2021 13:51:56 +0100 Message-ID: Subject: Re: [PATCH v1 1/2] gpio: tegra: Fix wake interrupt To: Dmitry Osipenko Cc: Thierry Reding , Jonathan Hunter , Laxman Dewangan , Linus Walleij , Matt Merhar , linux-tegra , linux-gpio , LKML Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jan 12, 2021 at 2:30 PM Dmitry Osipenko wrote: > > The GPIO bank wake interrupt setting was erroneously removed after > conversion to gpio_irq_chip, thus the wake interrupt programming is > broken now. Secondly, the wake_enb of the GPIO driver should be changed > only after the successful toggling of the IRQ wake-state. Restore the wake > interrupt setting and the programming order. > > Fixes: efcdca286eef ("gpio: tegra: Convert to gpio_irq_chip") > Signed-off-by: Dmitry Osipenko > --- > drivers/gpio/gpio-tegra.c | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c > index b8a4fd07c559..6c79e9d2f932 100644 > --- a/drivers/gpio/gpio-tegra.c > +++ b/drivers/gpio/gpio-tegra.c > @@ -541,6 +541,7 @@ static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) > struct tegra_gpio_bank *bank; > unsigned int gpio = d->hwirq; > u32 port, bit, mask; > + int err; > > bank = &tgi->bank_info[GPIO_BANK(d->hwirq)]; > > @@ -548,14 +549,23 @@ static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) > bit = GPIO_BIT(gpio); > mask = BIT(bit); > > + err = irq_set_irq_wake(tgi->irqs[bank->bank], enable); > + if (err) > + return err; > + > + if (d->parent_data) { > + err = irq_chip_set_wake_parent(d, enable); > + if (err) { > + irq_set_irq_wake(tgi->irqs[bank->bank], !enable); > + return err; > + } > + } > + > if (enable) > bank->wake_enb[port] |= mask; > else > bank->wake_enb[port] &= ~mask; > > - if (d->parent_data) > - return irq_chip_set_wake_parent(d, enable); > - > return 0; > } > #endif > -- > 2.29.2 > Applied, thanks! Bartosz