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Date:   Tue, 19 Jan 2021 15:12:43 +0100
From:   Thierry Reding <thierry.reding@gmail.com>
To:     JC Kuo <jckuo@nvidia.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>
Cc:     gregkh@linuxfoundation.org, robh@kernel.org, jonathanh@nvidia.com,
        kishon@ti.com, linux-tegra@vger.kernel.org,
        linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, nkristam@nvidia.com,
        Thierry Reding <treding@nvidia.com>, linux-clk@vger.kernel.org
Subject: Re: [PATCH v6 02/15] clk: tegra: Don't enable PLLE HW sequencer at
 init
Message-ID: <YAbo2574CnMB+UuU@ulmo>
References: <20210119085546.725005-1-jckuo@nvidia.com>
 <20210119085546.725005-3-jckuo@nvidia.com>
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On Tue, Jan 19, 2021 at 04:55:33PM +0800, JC Kuo wrote:
> PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
> power sequencers' output to enable/disable PLLE. PLLE hardware power
> sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
> are enabled.
>=20
> Signed-off-by: JC Kuo <jckuo@nvidia.com>
> Acked-by: Thierry Reding <treding@nvidia.com>
> ---
> v6:
>    no change
> v5:
>    no change
> v4:
>    no change=20
> v3:
>    no change
>=20
>  drivers/clk/tegra/clk-pll.c | 12 ------------
>  1 file changed, 12 deletions(-)

Michael, Stephen,

here's patch 2 of the hardware sequencer series that would need an
Acked-by so that it can go through a different tree.

Thanks,
Thierry

>=20
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> index c5cc0a2dac6f..0193cebe8c5a 100644
> --- a/drivers/clk/tegra/clk-pll.c
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw =
*hw)
>  	pll_writel(val, PLLE_SS_CTRL, pll);
>  	udelay(1);
> =20
> -	val =3D pll_readl_misc(pll);
> -	val &=3D ~PLLE_MISC_IDDQ_SW_CTRL;
> -	pll_writel_misc(val, pll);
> -
> -	val =3D pll_readl(pll->params->aux_reg, pll);
> -	val |=3D (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
> -	val &=3D ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
> -	pll_writel(val, pll->params->aux_reg, pll);
> -	udelay(1);
> -	val |=3D PLLE_AUX_SEQ_ENABLE;
> -	pll_writel(val, pll->params->aux_reg, pll);
> -
>  out:
>  	if (pll->lock)
>  		spin_unlock_irqrestore(pll->lock, flags);
> --=20
> 2.25.1
>=20

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