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[23.128.96.18]) by mx.google.com with ESMTP id z12si535707edc.117.2021.01.19.23.36.36; Tue, 19 Jan 2021 23:36:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b="Qx/HozEu"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728909AbhATHfW (ORCPT + 99 others); Wed, 20 Jan 2021 02:35:22 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:11182 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728750AbhATHfM (ORCPT ); Wed, 20 Jan 2021 02:35:12 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Tue, 19 Jan 2021 23:34:31 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 20 Jan 2021 07:34:28 +0000 Received: from jckuo-lt.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 20 Jan 2021 07:34:25 +0000 From: JC Kuo To: , , , , , , CC: , , , , , , JC Kuo , Thierry Reding Subject: [PATCH v7 02/14] clk: tegra: Don't enable PLLE HW sequencer at init Date: Wed, 20 Jan 2021 15:34:02 +0800 Message-ID: <20210120073414.69208-3-jckuo@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210120073414.69208-1-jckuo@nvidia.com> References: <20210120073414.69208-1-jckuo@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1611128071; bh=1qxLHnWZ76Ctb3+TZ1NgN5gqXaf56lnLK3e6zE/Vu0w=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=Qx/HozEu1Fs4vXqLD1M9MlC+sQGVEUT8Ltd4PO6MQY/0EACh64MX+Hw0qyX1sYlzR D6gjGahxxmeaRAGaD4rUqlO3GsGeMPoshitO/H4dPIR9VC8Q+aJ22wpTFwEZ9e5J8X 0NCVmgr3drzu+L+0dDdR1+woCMTLp5+d8sTaBBZpmpm5fIZxDIZa7/4uS9lXvfR4i8 53b8v4Xzxxp41qthDwQIB7ttuLStOHK2kevVkSIpoyrv6p9sAzrYxDI3g3HGrcGI1q DoriKE6n6qJ1hhR2zs07QNSo2cg1C3NrRii/9qZkz1Ab1rtawUJ7PQI+isl6RCAT46 fDP0yOXRygcoQ== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware power sequencers' output to enable/disable PLLE. PLLE hardware power sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers are enabled. Signed-off-by: JC Kuo Acked-by: Thierry Reding --- v7: no change v6: no change v5: no change v4: no change=20 v3: no change drivers/clk/tegra/clk-pll.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c5cc0a2dac6f..0193cebe8c5a 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *h= w) pll_writel(val, PLLE_SS_CTRL, pll); udelay(1); =20 - val =3D pll_readl_misc(pll); - val &=3D ~PLLE_MISC_IDDQ_SW_CTRL; - pll_writel_misc(val, pll); - - val =3D pll_readl(pll->params->aux_reg, pll); - val |=3D (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); - val &=3D ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); - pll_writel(val, pll->params->aux_reg, pll); - udelay(1); - val |=3D PLLE_AUX_SEQ_ENABLE; - pll_writel(val, pll->params->aux_reg, pll); - out: if (pll->lock) spin_unlock_irqrestore(pll->lock, flags); --=20 2.25.1