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[23.128.96.18]) by mx.google.com with ESMTP id x12si420878ejw.662.2021.01.19.23.37.19; Tue, 19 Jan 2021 23:37:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=aLYOMek1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728742AbhATHfL (ORCPT + 99 others); Wed, 20 Jan 2021 02:35:11 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:11131 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725320AbhATHfF (ORCPT ); Wed, 20 Jan 2021 02:35:05 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Tue, 19 Jan 2021 23:34:21 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 20 Jan 2021 07:34:20 +0000 Received: from jckuo-lt.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 20 Jan 2021 07:34:17 +0000 From: JC Kuo To: , , , , , , CC: , , , , , , JC Kuo Subject: [PATCH v7 00/14] Tegra XHCI controller ELPG support Date: Wed, 20 Jan 2021 15:34:00 +0800 Message-ID: <20210120073414.69208-1-jckuo@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1611128061; bh=uOdbNQDHFphc5P3H7s1GI8rw4bk0BmhJ4MSxSm3v0Ak=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:MIME-Version: X-NVConfidentiality:Content-Transfer-Encoding:Content-Type; b=aLYOMek18a7ucfsQGiFUUqGVgAgTr22y3t4wlyhKYWiWALM+5o107qtAfC0HwA8tQ efjqgm5qxKfKu3mSLPt24gUZ/k+Fz3CmcRs2Y8vl/56MV4kJNrVP+P4PyztwX1rXPW ecUN//Gg5xTVTavAHd1i4nhFwSx3JF/skgqVtZTNc5wdSBQoSQlim6Bq8FhqKnsmLY uR+kvcKtBciZB0Q6rUrLZGizng3ZhR9XMURWNfjI/GKuEf7Xbdpkq+28RECdDGGpI4 zile11sDw6g0pdXTtcxggBD7OFOx008373k/zFM6fYsuTZe7N35ckTLWH3wdsRuKIB 70tpsKjG84GCg== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra XHCI controler can be placed in ELPG (Engine Level PowerGated) state for power saving when all of the connected USB devices are in suspended state. This patch series includes clk, phy and pmc changes that are required for properly place controller in ELPG and bring controller out of ELPG. JC Kuo (14): clk: tegra: Add PLLE HW power sequencer control clk: tegra: Don't enable PLLE HW sequencer at init phy: tegra: xusb: Move usb3 port init for Tegra210 phy: tegra: xusb: Rearrange UPHY init on Tegra210 phy: tegra: xusb: Add Tegra210 lane_iddq operation phy: tegra: xusb: Add sleepwalk and suspend/resume soc/tegra: pmc: Provide USB sleepwalk register map arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop dt-bindings: phy: tegra-xusb: Add nvidia,pmc prop phy: tegra: xusb: Add wake/sleepwalk for Tegra210 phy: tegra: xusb: Tegra210 host mode VBUS control phy: tegra: xusb: Add wake/sleepwalk for Tegra186 usb: host: xhci-tegra: Unlink power domain devices xhci: tegra: Enable ELPG for runtime/system PM .../phy/nvidia,tegra124-xusb-padctl.txt | 1 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + drivers/clk/tegra/clk-pll.c | 12 - drivers/clk/tegra/clk-tegra210.c | 53 +- drivers/phy/tegra/xusb-tegra186.c | 558 ++++- drivers/phy/tegra/xusb-tegra210.c | 1889 +++++++++++++---- drivers/phy/tegra/xusb.c | 92 +- drivers/phy/tegra/xusb.h | 22 +- drivers/soc/tegra/pmc.c | 94 + drivers/usb/host/xhci-tegra.c | 613 ++++-- include/linux/clk/tegra.h | 4 +- include/linux/phy/tegra/xusb.h | 10 +- 12 files changed, 2784 insertions(+), 565 deletions(-) v5 "phy: tegra: xusb: tegra210: Do not reset UPHY PLL" is moved into v6 "phy: tegra: xusb: Rearrange UPHY init on Tegra210" --=20 2.25.1