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Wed, 20 Jan 2021 14:41:14 +0000 Date: Wed, 20 Jan 2021 08:41:11 -0600 From: Yazen Ghannam To: Borislav Petkov Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Smita.KoralahalliChannabasappa@amd.com, wgh@torlan.ru Subject: Re: [PATCH] EDAC/AMD64: Update scrub register addresses for newer models Message-ID: <20210120144111.GB1385775@yaz-nikka.amd.com> References: <20210116143353.7576-1-Yazen.Ghannam@amd.com> <20210118193112.GF30090@zn.tnic> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210118193112.GF30090@zn.tnic> X-Originating-IP: [165.204.78.2] X-ClientProxiedBy: SN4PR0701CA0038.namprd07.prod.outlook.com (2603:10b6:803:2d::31) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-nikka.amd.com (165.204.78.2) by SN4PR0701CA0038.namprd07.prod.outlook.com (2603:10b6:803:2d::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3784.12 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?QEEvgKuNbJZZQMF6otjxW2hiQq2mAHlUPXmY2/KiXVWHtmDjRnRbegdswLE4?= =?us-ascii?Q?R1pE4aXm1gFlHciEevNv/i3gXl9widpgVkV1LN1Kkk7l1XKfSDppiJ2WZYdP?= =?us-ascii?Q?uqtXb2RHNhCHZwYPTnKkZDQVvgwwdAdVmC0IVmgSwxWiWpPWVudLlzrGdFEX?= =?us-ascii?Q?ZUWAMqqlPVrqWc9jPOESzr+GF926gu8KWPxiziWUNu4//ZYrNp09cIJGbMKD?= =?us-ascii?Q?VEU0WfT6EooF7jKVtseHTi1SxRJHSdDERYkJ8tWG5aBn0rz6v6IIeTS3NJVd?= =?us-ascii?Q?mMoF3XMj5/fJd3JV7hzPju9WHR3bHLziA/jczzyXav1i5yweD3MZLDWWQGh7?= =?us-ascii?Q?75a/aF1l4n31o/LWpcsrXfa1fgGvznHhLmZpCMu3dcX+ivYGFnbbv/d8x3TG?= =?us-ascii?Q?ktFbObQdlM9aLtb6EDek0JfF4p2QyxU2Gxts7VOdo/rva9fcGounqkT7Jirw?= =?us-ascii?Q?B4pvvNep//N6N/tojhVGK9IBWlE79beINyPD/sBbbwfFX2cIyfhsUcT+6/UU?= =?us-ascii?Q?IkfimYjKmTeoGeRYkpJdczgF6x/XzskjciVeFjiK85CjrLgvtDSRTKLaS9X7?= =?us-ascii?Q?o3ohZ5dHX3r5R21t3/XlxcmhfmWMv30oS3Ej4zFfnVIieSNLfKuPe9z8o/q7?= =?us-ascii?Q?l9uGGma4sqnf7ImdO8G0CdNdLEaQka9dwnBl7qxd3yh/qBfpFyQQaSHaz6R2?= =?us-ascii?Q?Qz79Bwg6IHWLhUeNdwh3EUmpGeOG8v5fgduktXjuDkTX4u2BuBPhEbcmYmai?= =?us-ascii?Q?bDzamMmTteIXNXLYO0QXan2E4X96i8J+R3VMWQvvW07/GTkrVw4k0NUR6HDZ?= =?us-ascii?Q?0jj7QBAKUnVmVrkdmnkOJ7s1vJ1YPICHM7MhLQmgUle+dmwOR9CUlQ5A1mmY?= =?us-ascii?Q?PjKCCiBSxZ1pfjiU3OCE3b4DpfqAsa2s3wOh7eufTJhdHaeTNJHW+8SF2GHf?= =?us-ascii?Q?AjLZnv8iWof4JAP2J3c1gvNr5YiUcURIZxhvUaAbXRTEIvTx4V5fYKFbDuQ3?= =?us-ascii?Q?o95z?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a40be0d5-a71d-4dd1-0279-08d8bd51701f X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2021 14:41:14.6874 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cYJzQAlMt+OyCNbT1J0e4HsP9sbAzmwMB/zhoPuUooUffHIBsrGdSUVs3vDzrVxR4vIuK8yE+knHzlKdLV/HeQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3218 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 18, 2021 at 08:31:12PM +0100, Borislav Petkov wrote: > On Sat, Jan 16, 2021 at 02:33:53PM +0000, Yazen Ghannam wrote: > > +static struct { > > + u32 base, limit; > > +} f17h_scrub_regs = {F17H_M30H_SCR_BASE_ADDR, F17H_M30H_SCR_LIMIT_ADDR}; > > Why not make this part of struct amd64_umc so that you can access them > through pvt->umc? > We have a struct amd64_umc per channel, so putting these fixed values there seemed redundant. Would you mind if we put this in struct amd64_family_type? We can then set the values per family/model group like we do with the max_mcs. Thanks, Yazen