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Date:   Wed, 20 Jan 2021 18:18:08 +0000
From:   Catalin Marinas <catalin.marinas@arm.com>
To:     Marc Zyngier <maz@kernel.org>
Cc:     linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu,
        linux-kernel@vger.kernel.org, Will Deacon <will@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        David Brazdil <dbrazdil@google.com>,
        Alexandru Elisei <alexandru.elisei@arm.com>,
        Ard Biesheuvel <ardb@kernel.org>,
        Jing Zhang <jingzhangos@google.com>,
        Ajay Patil <pajay@qti.qualcomm.com>,
        Prasad Sodagudi <psodagud@codeaurora.org>,
        Srinivas Ramana <sramana@codeaurora.org>,
        James Morse <james.morse@arm.com>,
        Julien Thierry <julien.thierry.kdev@gmail.com>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        kernel-team@android.com
Subject: Re: [PATCH v4 02/21] arm64: Fix outdated TCR setup comment
Message-ID: <20210120181807.GB17952@gaia>
References: <20210118094533.2874082-1-maz@kernel.org>
 <20210118094533.2874082-3-maz@kernel.org>
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On Mon, Jan 18, 2021 at 09:45:14AM +0000, Marc Zyngier wrote:
> The arm64 kernel has long be able to use more than 39bit VAs.
> Since day one, actually. Let's rewrite the offending comment.
> 
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
>  arch/arm64/mm/proc.S | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index 1f7ee8c8b7b8..ece785477bdc 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -464,8 +464,8 @@ SYM_FUNC_START(__cpu_setup)
>  #endif
>  	msr	mair_el1, x5
>  	/*
> -	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
> -	 * both user and kernel.
> +	 * Set/prepare TCR and TTBR. TCR_EL1.T1SZ gets further
> +	 * adjusted if the kernel is compiled with 52bit VA support.

I think both T0SZ and T1SZ get updated based on a mismatch between the
kernel configuration and the hardware support. Anyway, I'm not asking
for a detailed comment here, so:

Acked-by: Catalin Marinas <catalin.marinas@arm.com>